Pooling CPU memory for LLM inference; high-bandwidth chiplet interconnects for adv. packaging; dense edge architectures; spiking neuromorphic HW; GAAFETs; defective chip detection; multi-chiplet NPUs for autonomous driving.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Pie: Pooling CPU Memory for LLM Inference | UC Berkeley |
| High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions | TSMC |
| System-Technology Co-Optimization for Dense Edge Architectures using 3D Integration and Non-Volatile Memory | imec, INESC-ID, Université Libre de Bruxelles, et al. |
| The backpropagation algorithm implemented on spiking neuromorphic hardware | University of Zurich, ETH Zurich, Los Alamos National Laboratory, Royal Institution, London, et al. |
| Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height | imec, Huawei Technologies and Global TCAD Solutions |
| Detection of defective chips from nanostructures with a high-aspect ratio using hyperspectral imaging and deep learning | Samsung |
| Performance Implications of Multi-Chiplet Neural Processing Units on Autonomous Driving Perception | UC Irvine |
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