PDN for CIM; accelerating OTA circuit design; inter-chiplet interconnects; wireless multi-chip AI accelerators; oxygen plasma treatment to enhance Cu-Cu bonding; indium tungsten oxide TFTs; wafer-scale computing for LLMs.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Co-Optimization of Power Delivery Network Design for 3D Heterogeneous Integration of RRAM-based Compute In-Memory Accelerators | Georgia Tech |
| Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables | University Minnesota and Cadence |
| PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies | ETH Zurich and University of Bologna |
| WaferLLM: A Wafer-Scale LLM Inference System | University of Edinburgh and Microsoft Research |
| Exploring the Potential of Wireless-enabled Multi-Chip AI Accelerators | Universitat Politecnica de Catalunya |
| Understanding and Optimizing Oxygen Plasma Treatment for Enhanced Cu-Cu Bonding Application | Seoul National University of Science and Technology |
| Thermally Dependent Metastability of Indium-Tungsten-Oxide Thin-Film Transistors | Rochester Institute of Technology and Corning R&D Corporation |
Find all technical papers here.
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