Chip Industry Technical Paper Roundup: Jan. 7

Processing-in-DRAM; co-packaged optics; SOT-MRAM development; efficient wearables; open-source heterogeneous SoCs for AI; Cu–Cu bonding reliability; multifunctional 2D FETs; wafer defect classification.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Memory-Centric Computing: Recent Advances in Processing-in-DRAM ETH Zurich
Next generation Co-Packaged Optics Technology to Train & Run Generative AI Models in Data Centers and Other Computing Applications IBM
Recent progress in spin-orbit torque magnetic random-access memory imec
Enabling Efficient Wearables: An Analysis of Low-Power Microcontrollers for Biomedical Applications EPFL
Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience University of Bologna
Ammonia Plasma Surface Treatment for Enhanced Cu–Cu Bonding Reliability for
Advanced Packaging Interconnection
Myongji University
Multifunctional 2D FETs exploiting incipient ferroelectricity in freestanding SrTiO3 nanomembranes at sub-ambient temperatures Penn State University and University of Minnesota
Semi-Supervised Learning with Wafer-Specific Augmentations for Wafer Defect Classification Korea University

Find all technical papers here.



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