Estimating voltage drop with ML; BEOL-compatible 3D logic; wafer level SoC test; ultrathin film that preserves electrical properties; RISC-V multicore and GPU SoC platform for safety critical space; protecting ASLR against microarchitectural attacks; low-temp manufacturing process for TFTs.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogate | KTH Royal Institute of Technology and Ericsson Research |
| Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock | Stanford University, Intel Corporation and Carnegie Mellon University |
| Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip | Inha University and Teradyne |
| Strain-free thin film growth of vanadium dioxide deposited on 2D atomic layered material of hexagonal boron nitride investigated by their thickness dependence of insulator–metal transition behavior | Osaka University and National Institute for Materials Science |
| A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems | Universitat Politecnica de Catalunya and Barcelona Supercomputing Center |
| Oreo: Protecting ASLR Against Microarchitectural Attacks | MIT |
| Low-temperature pressure-assisted liquid-metal printing for β-Ga2O3 thin-film transistors | UCSD and National Tsing Hua University |
Find more semiconductor research papers here.
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