Memory system benchmarking, simulation; decoder-only transformer models; quantum chiplets; AI workloads on MCM accelerators; FeFETS for in-memory computing; HW security eval board; on-chip photonics cytometer.
New technical papers added to Semiconductor Engineering’s library this week.
| Technical Paper | Research Organizations |
|---|---|
| A Mess of Memory System Benchmarking, Simulation and Application Profiling | Barcelona Supercomputing Center, Unversitat Politecnica de Catalunya, and Micron |
| Lean Attention: Hardware-Aware Scalable Attention Mechanism for the Decode-Phase of Transformers | Microsoft |
| MECH: Multi-Entry Communication Highway for Superconducting Quantum Chiplets | UC San Diego, UC Santa Barbara, and Cisco Quantum Lab |
| SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Accelerators | University of California Irvine |
| Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads | Purdue University |
| EFFLUX-F2: A High Performance Hardware Security Evaluation Board | Nanyang Technological University (Singapore) and Indian Institute of Technology Jodhpur |
| On-chip flow cytometer using integrated photonics for the detection of human leukocytes | imec and Sarcura GmbH |
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