Collaboration Widens Among Big Chip Companies

Experts at the Table: Semiconductor Engineering sat down to discuss the growing need for collaboration among equipment and tools vendors, the impact of systems companies and increases in complexity, and how to handle a push for more customization while controlling costs, with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle solutions at Siemens EDA. What follows are excerpts of that conversation, which was held in front of a live audience at the recent SEMI Industry Strategy Symposium. (Find part two of this discussion here). 

SE: Across the chip industry we’ve been pushing the limits of Moore’s Law for the past couple process nodes, which is why we’re seeing an emphasis on advanced packaging and chiplets. But we’re also seeing new types of companies driving these changes, and a push for more customized solutions? This seems to point toward deeper collaboration than in the past. What do you see changing and how will this play out over time?

Fried: Throughout most of my career, and most of Moore’s Law, we were able to compartmentalize the industry so that each of the individual contributors in the value chain or supply chain could optimize their particular piece of the chain, and we would end up with an optimized product or system at the other end. So we have ASML doing lithography, and Lam Research looking at deposition and etch. And in the fab, because we both optimized our individual processes as much as possible, we were able to continue the scaling roadmap for many years. But we passed the point 15 or 20 years ago where lithography and etch could be completely independent. We needed to collaborate and understand the adjacencies in the fab. Now, with the most advanced technologies at the leading edge of scaling, we’ve gotten to the point where we need to understand adjacencies much further afield from our specialization. In order to do our own particular part of the business better, we must have a much deeper understanding of the adjacencies and the process, and that reaches far beyond litho and etch optimization to design technology optimization systems, and product design optimization. So for those adjacencies, the optimization and collaboration required have expanded dramatically in the last couple years.

Van den Hove: Cooperation is more important than ever, and it will become even more important, especially when driving technology to these new extremes. In the past we had well-defined roles and received all the benefits of scaling simultaneously. But now we are hitting some of these famous walls, like the performance wall, where it’s just not going to work anymore. As a result, we have to develop technology solutions to address some of these limitations, and they will come from continued shrinking. So ASML will be enabling that for the next decade in lithography, but it will have to happen with new devices, new device architectures, and new interconnect schemes, like putting the power delivery system on the backside of the wafer. It will come with heterogeneous integration, chip-to-chip stacking through various techniques like micro-bumping or hybrid approaches. We have a wide variety of options, and this is good because one of the other major trends is that there is not going to be one solution for every application. What is good for Apple may not be good for high-performance computing, or may not be optimal for automotive. We will need to have much more collaboration in the future across the value chain, bringing system know-how closer to technology development.

Gupta: Collaboration for EDA has been with EDA companies first, and with foundries second. Our goal has been to model the physics accurately, then translate that into rules, so that up front in the design you can work with those rules. Design is followed by production, and production is followed by a system view of the chip. What’s changing fundamentally going forward is that now we are being asked by systems companies to measure the performance of a chip, not just in the release of GDS II to manufacturing, but all the way into the system. Collaboration now extends to foundry partners, to production partners, as well as to the end customers. What you do for one systems company might be different from another, so we have to collaborate with all of these customers differently.

van den Brink: Throughout a significant part of my career, Dennard scaling was the primary way to drive performance, power, size, and cost, because you could get everything automatically. That stopped about 15 years ago. Shrinking is still a force, because making things smaller is driving down costs. But you don’t automatically get improvements in performance and power. Being a lithographer, we never owned the total solution, and we never talked about it. We never engaged in masks, even though without a mask lithography doesn’t exist. But over time, we have been talking with other tech companies about aligning processes to increase productivity and value for the customer. So there’s always a drive to look to the bigger picture. If a mask can make smaller features, there’s no need for an industry reset, and 50 years ago we introduced a lithographic approach. Now, the cost of the product is the main issue, so we are using multiple tools to make a correction. We always push the boundaries, and moving forward this will become more complex because now customers want something more specific. They want memory devices bonded to the core. The next steps will require us to work with our customers, our co-solutions suppliers, and suppliers of this bonding process, to understand how to create value in this equation.

SE: In addition to classic chipmakers competing for a slot, we’re also seeing the rise of companies like Google, Apple, and Amazon designing their own chips. In the case of some of these companies, these chips are being used internally and we don’t ever see them. How does that affect collaboration?

Fried: The systems are being optimized and the workloads are being optimized, so all the components that contribute to that workload performance need to be aligned. The companies designing their own silicon for their own systems are using a specific set of chip specifications with a set of software specifications to hit certain workload optimization. Those chip specifications need to be aligned with the technology offering, which goes all the way down to the foundry. And that may be very different from other chip specifications in existence. The foundry needs to align the performance of individual processes to hit that. On the equipment side of the business, because we need to have a general-purpose solution that meets all of these requirements, we’re looking to optimize for more specific applications and workflows. At the end of the day, it’s the same set of communication alignment and collaboration, from top to bottom. There’s just more different instances of what’s happening now because of this bifurcation. It’s gotten challenging to do a general-purpose optimization in any of these areas and still have enough value in the specialization and in the bifurcation of the roadmap. So we’re all contributing to that, and we’re all aligning in multiple dimensions.

Gupta: It’s a challenge, for sure. With bespoke silicon, there are still some things that apply to all customers for specific nodes. Systems companies are designing at the same technology nodes and going to the same foundries as general-purpose customers, but their concepts and their methodologies are different. When you think back to designing the first TPU, there were specific requirements for EDA that we had to contend with that didn’t exist in the marketplace. That leads to early access programs. And if I had to pick one thing that’s very different because of this bifurcation, it’s the rise of those early access programs where we are working directly with these customers. That creates stress on R&D for any EDA company, of course, and the timeline is shorter. But we can work with customers to figure something out.

Van den Hove: We’ve seen these trends in the past where we’ve had specialization in the industry by players and foundries. This is why you need a variety of options, and you have to pick the right options to get the best use out of your device. That requires a different way of thinking, and it’s why many of these systems companies are entering into the chip domain. They want to understand this technology. What we’re seeing with many of our products is that we have strong interest by these systems companies to understand the technology options and come up with the best architectures. That’s needed to accelerate the innovation process across the ecosystem and the value chain because things are becoming so complicated. If we bring innovation over from one layer of the value chain to the next, it’s too slow. We’ve seen that in the automotive industry over the last few years, where there is a massive need for high-performance semiconductors. They need to start the innovation process much earlier.

SE: But there are multiple processes at each node, in addition to half-nodes and other nodelets. Does the same equipment work across all of them?

van den Brink: There are different boundaries, but the requirements are similar. The challenge, though, is how we move forward. The need for innovation is still there, but it will happen at a slower pace than before. And costs will go up, not down, so we have to make it up somewhere else. So if you’re looking at the performance of the device, and the total system, then you can justify the price. But everyone has to have a clear understanding of the value they bring. In the past, companies like IBM and Philips and TI did everything themselves. But as wages and other costs go up, the value proposition changes. So now you have to decide what you can delegate and understand how that plays out. And for the industry, given the increase in complexity moving forward, you have to readjust on every level in order to create value.

Related
Big Changes Ahead For Chip Technology And Industry Dynamics
How customization, complexity, and geopolitical tensions are upending the global status quo (part 2 of above discussion).