Connecting Wafer-Level Parasitic Extraction And Netlisting

The semiconductor technology simulation world is typically divided into device-level TCAD (technology CAD) and circuit-level compact modeling. Larger EDA companies provide high-level design simulation tools that perform LVS (layout vs. schematic), DRC (design rule checking), and many other software solutions that facilitate the entire design process at the most advanced technology nodes. In this blog, I’d like to focus on the design of silicon-level connections between devices and wires in the backend-of-line (BEOL). These connections run across chips and connect various nodes to each other, and ultimately form circuits on the device.

A netlist is a description of the connections within an electronic circuit. It includes a list of the electronic elements and connected nodes within that circuit. A typical netlist includes all the extracted parasitic resistances and capacitances that are part of a circuit layout. Identifying the specific layers that define the transistors and metal wiring is critical in accurately calculating these parasitic values. The resulting parasitic R’s and C’s, between every node (port) and across every net (wire), forms a parasitic netlist. A netlist and associated parasitic values are normally brought into a compact modeling platform (e.g. Spice) for subsequent circuit-level simulation.

The SEMulator3D process modeling platform provides both RC extraction and netlisting capabilities. This combination of capabilities enables fast and accurate netlist generation, including parasitic value extraction, and allows the netlist to be directly imported into a compact model. A typical netlist output from SEMulator3D is shown in Figure 1.

Fig. 1. Typical netlist output showing parasitic resistances and their node connections.

Using a parasitic netlist, a circuit designer can import the netlist of R’s and C’s into their compact model and verify the circuit layout and operation. A realistic understanding of the circuit environment, along with the performance implications of parasitic RC effects, can be analyzed after importing the RC netlist data into a compact model. Ultimately, this helps determine if the circuit will function within the targeted specifications.

The SEMulator3D software platform also provides an accurate 3D process model of a specified layout manufactured using pre-defined process steps. Figure 2 displays an example of a layout built using SEMulator3D, along with a portion of the resulting 3D structure revealing the connection between transistors and metal wires. The goal of netlist extraction is to extract parasitic R’s and C’s at both the transistor and metal levels. The netlist modeling infrastructure in SEMulator3D includes transistor identification based upon layout mask levels, a Name Layer Step that identifies the conductive materials, and port identification and placement which defines the connection points between conductors and the transistor source/drain.

Fig. 2. Circuit layout on left and resulting transistor and metal wiring shown on right. External ports are shown in blue.

A resulting netlist structure from SEMulator3D, with all the required ports (identified in blue), is shown in Figure 3. The electrical view of the structure, which identifies the netlist structural components that comprise the final netlist output, is also shown in Figure 3.

Fig. 3. Netlist extracted structural components (left) with ports identified in blue. The right figure is the resulting electrical set of components that make up the netlist of R’s and C’s.

The netlist file in SEMulator3D can be written out to a .txt file for easy import into any compact model. A partial portion of the netlist file is shown in Fig. 4.

Fig. 4. Final netlist output.

Standard RC extraction and full netlist extraction, at the silicon process level, is provided within SEMulator3D. The ability to link an accurate process flow (including each process module step and parameter) to the parasitic RC netlist is invaluable during process development. Designers can obtain a comprehensive and direct understanding of how each process step effects higher-level circuit performance and function, to avoid the time and cost of silicon-based learning.