DFM And Multipatterning

Semiconductor Engineering sat down to discuss DFM at advanced nodes with Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics; Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries; David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics; Ya-Chieh Lai, engineering director for DFM/CLS silicon signoff and verification at Cadence; and Soo Han Choi, a member of the senior staff for foundry R&D in Synopsys’ SoC design group. What follows are excerpts of that conversation.

SE: Will silicon photonics be focused inter-chip rather than intra-chip?

Abercrombie: That’s where it will start. But can it migrate into the die eventually? Probably.

Kye: Today if you look at an SoC chip, at the die level there are already a lot of things happening. Memory and I/O are all interconnected very locally. If it goes up to three or four levels connected together, it’s similar to 2.5D. There isn’t much difference. It’s just whether it’s at a lower level or a higher level.

SE: Do you think 2.5D will solve some of these problems, or will it just spread them out across multiple chips?

Lin: There is an inflection point because there are quadruple and triple masks. But 2.5D has its own challenges with thermal and stress.

Kye: We don’t see an inflection point yet for 2.5D, but there are some examples of CPUs and GPUs being integrated. Those are different specs, but they’re being connected together in one die, not separate dies. We don’t have good examples of 2.5D yet. But at the SoC level there is the logic core, SRAM memory, analog—all integrated. Whether you call this 2.5D or not—there isn’t any real boundary.

SE: You’re looking at it with metal layers as your stack and the interconnect instead of an interposer, right?

Kye: Yes, at the lower level.

Lai: There is progress.

Abercrombie: The tools are ready. It’s just a matter of the need. We thought it was going to happen tomorrow, like everyone else. We’re just waiting for the adoption.

SE: Where does DSA fit into this? It’s been promised as an alternative to EUV, but where is it?

Kye: The cost effectiveness is critical. Double patterning was 50% of scale when we started. DSA is a different approach. It requires special chemistry. DSA is not starting from a known spec. We have to understand where the defects are. We also don’t have the cost information for that. The infrastructure needs to be there, but we have not invested like we have with EUV. There are so many unknowns we cannot estimate the cost.

Lai: It’s a cool technology. It requires a lot of changes on the EDA side. The design methodology needs a rethink to make it work. That’s a big step to take. It’s one thing to have a process. Then you need a methodology to do it. But that methodology is different enough you need early adopter designers to work with it.

Kye: DSA requires a guideline. It’s not necessarily friendly to the foundry business. It’s more friendly to high performance, not the foundry. It will probably come to DRAM, flash memory or high-performance logic.

Lai: There are a lot of restrictions. There is an alphabet of things you can do. There’s an idea there is only a limited set of patterns you can use for your design, and that’s going to affect a lot of things.

SE: Are we getting to the point where we need more design rules at 14nm, 10nm and maybe 7nm? And is that a change, or is it business as usual at advanced process nodes?

Lai: It’s already happening.

Abercrombie: Yes. We’re already seeing restricted layout. SADP and DSA will be much more restricted layout. It’s already there at the gate level with line cuts—they’re one-directional cuts. You cannot take the design community from wherever you are to the next node in one step. You have to get there a little bit at a time. You add a few layers, and then a few more layers with more restrictions, and after a time they adapt. We will end up in a much more restrictive design phase.

Lai: We already see it. If you look at the layout, as it goes from one node down to the next. With poly layout there is a huge change between how it looks now.

Lin: Older management is all rules-driven. The younger generation have been pushing them. There are different methods for verifying the design at 14nm and 10nm. You need patterns to verify it. You have model-based things you have to run to get to signoff. There are multiple different types of applications. So the mindset is changing. It’s more receptive to that kind of methodology.

Abercrombie: Design verification is ahead of design implementation. We can verify by pattern, by restricted design rule versus complex unrestricted design rule. It’s implementing by pattern library that’s a lot farther away than verifying by pattern library. How do you change the entire design methodology to say, ‘I don’t just draw by restricted rule. I create based on pattern.’ No such thing exists. How would you do that?

Kye: FinFET is already grating. At the routing level, it’s going to be grating, too. We have a couple layers for innovation. That’s what’s coming.

SE: Typically, though, as processes mature the restrictions soften. Are we getting to the point where that can’t change because there is too much complexity?

Abercrombie: That doesn’t seem to be the trend.

Kye: I don’t see that trend, either.

Abercrombie: That happens because designers push for more flexibility. Once they get comfortable with this gridded way of uniform design, and design implementation catches up with that approach, that push will go away.

Kye: It may happen at 14nm, but we have to push 10nm with even more restrictions. Node to node there are more restrictions.

Lin: The pattern library may be less restrictive as time goes on.

SE: There has been a push toward fully depleted SOI at 28nm. Is the industry starting to look backward toward older nodes to improve them?

Lin: There are performance and power tradeoffs.

Kye: It’s not really an advantage or disadvantage to stay at one node or move to another. It’s a different track. Whether people like one track or another is a choice. It’s not necessarily about the technology difference.

SE: EDA has been able to get 10X improvement per node for tools. Will those kinds of gains be available for future generations of chips?

Lin: We have to attract new engineers. It is getting harder and harder.

Lai: I would love to see more investment in EDA. EDA has been a tough place for people to invest in because the returns are uncertain.

Choi: Performance is important, but more important is accuracy—particularly with double patterning and triple patterning. For performance, that will take more time.

To view part one of this roundtable discussion, click here.