EDA Vendors Prepare For 7nm

It’s not too early to begin looking at design tools for the 7nm, even though the node is not expected to be production-ready until later this decade.

While still in the early stages, foundries already in development with leading EDA companies, even though the water remains murky at this point.

“7nm right now is in early definition, so we don’t know exactly what it will be,” observed Vassilios Gerousis, distinguished engineer at Cadence. “For example, there are foundries looking primarily at EUV, which will simplify EDA tools at least for the physical place and route. From others looking at the evolution of lithography, at 10nm we dealt with triple color on some layers. In 14nm we dealt with double color on some layers, which means double patterning or triple patterning, and at 10nm we also dealt with vias for the first time, which is the connection between metal layers that are also becoming double patterning. The question is whether lithography will evolve. If EUV does not come at 7nm, lithography may require us to do quadruple patterning, which means one layer could become 4 masks, essentially, or more.”

For Cadence, 14nm development is done. The company is working on 10nm development, which is reaching the alpha stage and the next beta stage, he noted, and expects advanced customers and foundries to be starting to look at 7nm at the same time.

“We have already started working with some of the foundries with 7nm. Like with EDA tools there are people working on current products and there are also engineers that are working on advanced products. It’s the same thing with silicon. People work on current products as well as advanced projects. There are some people starting on 7nm definition,” Gerousis said.

Swami Venkat, senior director of marketing, Galaxy Design Platform at Synopsys, observed that 7nm at this point is about leveraging the learnings of ‘older’ nodes.

Pointing to finFETs and the move to 20nm as major inflection points, he noted that with 20nm came double patterning and for the first time, the whole ecosystem had to deal with that technology. “Very closely following that was finFETs, and now at 16/14nm we are using a mix of all of this. Devices have become 3D now and there is double patterning, and obviously there has been a lot of work that we had to do in very tight collaboration with the foundries. What we noticed at these nodes is that our collaboration with foundries has been for a much longer period of time. Particularly with finFETs, even before that we were working with UC Berkeley to develop models — particularly SPICE models — and what we noticed is at 16nm/14nm our collaboration with foundries to bring a new node usually would take about 18 months or longer. At older nodes it might have been a year or less than a year.”

Collaboration with the foundries is much longer for nodes such as 7nm due to significant impact from a device and routing perspective, Venkat said.

When it comes to the sign-off and power analysis areas, Shekhar Kapoor, director of marketing, signoff extraction and power at Synopsys said, “These are clearly the areas where we are in deep collaboration with the foundries for the longest time and a lot of work has already gone into the 20nm technologies and finFET nodes. A lot of readiness is already there. From our point of view we are seeing no change. Customers continue to be interested in knowing more and more about the new technologies. We are in all those early discussions.”

As in the past, what is driving scaling down to 10nm and 7nm are performance and power, but there are new issues emerging for both of them. “There are two areas which foundries in particular are looking at the transistor side, which is the front end of line, and the interconnect (back end of line),” Kapoor said. “There is also the printability aspect, on the manufacturing side, which are all of the things done to achieve performance and be able to print them. Going back to 20nm, from a transistor point of view, what design engineers can do to increase mobility is heavily reliant on the manufacturing end. What this means for us is that we have to do the modeling of the new effects to provide the accuracy to correlate to silicon measurement, for example. On the interconnect side, it’s the same thing if they are continuing to use the current lithographic techniques —what do we do for variation modeling, for example. You see the same pattern in what needs to be done in the newer nodes, but you can imagine the complexity continues to increase because there are newer effects, newer parameters that you have to take into account.”

Making sure it works
By the time 7nm rolls around, hierarchical test is expected to be pervasive.

“Test is an interesting category in that we don’t necessarily develop solutions and tools for a particular node,” said Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics. “Unlike where you have a particular deck for a particular node, or particular rules or particular node requirements, test is more of an evolving field. In that sense it’s somewhat node agnostic, so we won’t create a particular test solution or capability for a particular node. It’s really more evolutionary. As things become more critical, become more difficult, you need improvements or enhancements or extensions of existing solutions to meet the needs of a new node or as certain things become more important at a new node.”

This became obvious when the industry first began working on finFETs at 16/14nm, and suddenly it became concerned with new defect types. “With 3D transistors, when you looked at the critical dimensions of a finFET for the first time, they were smaller than the actual resolution of the node itself and we are still dealing with that. So defect coverage became more critical at 16 and it is expected that it will stay this way at 10nm and 7nm,” he said.

At 16/14nm it was no longer enough to look at abstract fault models, a trend that certainly will continue down to 10nm and 7nm. New defect mechanisms for text coverage and pattern generation will be required. Specifically, test teams will target defects beyond the netlist and look at layout based expressions of defects, which Mentor Graphics refers to as cell-aware modeling. So instead of modeling defects in an abstract way, they are abstracted from the gate level (i.e., parasitic values extracted from the layout from each cell are used to model defects).“Instead of just relying on these traditional abstract gross ways of modeling defects, we need the ability to very explicitly define the conditions for the existence of a defect. That will become critical at 10nm and 7nm,” Pateras said.

Tied to this will be diagnostics and being able to understand the defects, particularly which ones are non-random and systematic in nature and which affect yield. At each new node, the ramp becomes more difficult, requiring a better understanding early in the development process of the defect mechanisms. That, in turn, needs to be fed back to the design side.

Who will move to 7nm?
A burning question for the tool providers on both the design and manufacturing side is which companies and applications will take advantage of 7nm first.

There is no doubt the first players in this market will be those with the highest volume and enough cost resiliency and a need for power to justify the investment.

“There will be a large segment that will move to finFETs, but there are also a lot of people that are either choosing the remain at 28nm or use some other established node,” said Venkat. “We see advanced designs being done at both these kinds of nodes, but in terms of who will really go to the smaller geometries, if this trend continues, the segment moving to finFETs will probably continue the march toward smaller geometries because of cost factors and new technologies that have to be dealt with. Average design teams cannot justify the move to these smaller nodes.”