Mask-wafer co-optimization for faster curvilinear ILT.
This talk by Leo Pang, Chief Product Officer of D2S, takes a look at a unique GPU-accelerated approach to curvilinear inverse lithography technology (ILT) and introduces mask-wafer co-optimization (MWCO) that enables writing curvilinear ILT for 193i on VSB or multi-beam machines in 12 hours.
Less precision equals lower power, but standards are required to make this work.
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design.
Ensuring that your product contains the best RISC-V processor core is not an easy decision, and current tools are not up to the task.
Wafer manufacturing and GPUs draw investment; 106 companies raise $2.8B.
Heterogenous integration depends on reliable TSVs, microbumps, vias, lines, and hybrid bonds — and time to digest all the options.
How prepared the EDA community is to address upcoming challenges isn’t clear.
Advanced etch holds key to nanosheet FETs; evolutionary path for future nodes.
Details on more than $500B in new investments by nearly 50 companies; what’s behind the expansion frenzy, why now, and challenges ahead.
From specific design team skills, to organizational and economic impacts, the move to bespoke silicon is shaking things up.
Less precision equals lower power, but standards are required to make this work.
New memory approaches and challenges in scaling CMOS point to radical changes — and potentially huge improvements — in semiconductor designs.
Open-source processor cores are beginning to show up in heterogeneous SoCs and packages.
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design.
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