ESD Co-Design For High-Speed SerDeS In FinFET Technologies

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, including the phase from the completion of the silicon wafer processing to when the device (die) is assembled in the system. To avoid yield loss due to ESD damage during this early phase, on-chip ESD protection measures are applied to provide a certain degree of ESD robustness. The component ESD withstand level is classified in the Charged Device Model [1] (CDM) and Human Body Model [2] (HBM) standards. The ESD targets of the device are set according to the required CDM and HBM levels and appropriate ESD protection measures are applied to ensure ESD robustness for all exposed device pins. When the exposed pins are data pins of high bitrate interfaces, such as high-speed SerDes, interference of the necessary ESD protection measures can deteriorate the speed performance. Besides, the so-called ESD design window, which is defined as the difference between the breakdown voltage of the devices and the supply voltage level, has become extremely small in the latest, most advanced (FinFET) technologies [3] . In order to yet meet the ESD targets for CDM and HBM, smart co-design of ESD protection with the SerDes transmitter circuit has become a necessity. In this white paper is firstly shown the problem in current FinFET technologies with classical protection methods and the need for enhanced (secondary) protection measures in transmitter circuits. Secondly, essential to meet the demands of high-speed SerDes interfaces, such as the Synopsys 224G and 112G Ethernet PHY IP and the Synopsys PCI Express® IP, are measures to minimize the capacitive load of the protections, which is accomplished by creating an intrinsic ESD robust transmitter. Next are discussed options to obtain optimal intrinsic robustness of the transmitter by ESD co-design, with possible limitations and pitfalls to be aware of. Finally a set of circuit topology and layout checks is proposed to verify ESD robust architectures and correct implementation.

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