Expand Your Semiconductor’s Market With Programmable Data Planes

In nearly every communication interface today, many challenges exist. Not only must networks manage high volumes of data traffic, they must also be highly aware of malicious data intrusions. With increasing data moving though these networks, combined with demand for faster response times and lower latency, high performance packet processors came into existence as these were the only mechanisms capable of handling data traffic at these speeds. To analyze high volumes of incoming serial data packets, techniques like Inband Network Telemetry (INT) were deployed to provide valuable insight into the network traffic. This allowed servers to understand the context and volume of traffic coming into the network, which can help mitigate congestion as well as quickly forward packets to the appropriate destination or IP.

Initially these mechanisms were heavily deployed in FPGAs, so much so that companies like Xilinx developed their own software tools for implementing popular programming languages, like P4 (Programming Protocol-Independent Packet Processors). FPGAs were perfect for these applications as everything related to communications interfaces were evolving. Not only the protocols and security threats, but also the architectures and algorithms to support these logarithmically increasing data rates.

But as it usually goes, once technologies like these mature, these solutions often move from expensive and power-hungry FPGAs to ASICs. Though there is one thing that is constant in communication interfaces, and that is change! So as the story continues, it forces ASIC companies to make very tough decisions…

The ASIC dilemma: Specialization vs. commoditization

Whenever ASICs are developed, every design and feature decision is highly scrutinized, as performance and die area are highly coveted design criteria. Of course, every company wants to build commoditized devices that can span across multiple applications and increase sales volumes. However, this increases cost and often limits performance. Thus, many ASIC companies steer toward specialized solutions that are high performing. This balance is a struggle that all chip companies deal with.

ASIC designers also have another challenge. To get to market on time, IP and algorithms are designed and taped out while communications protocol specifications are not fully ratified. This leaves no margin for design errors or little time for design allowance to develop additional features. Naturally, once these devices are released, the protocols, security threats, traffic management algorithms and competitors’ technology continue to evolve, limiting the product lifespan of these devices. Of course, this leads us back to considering FPGAs. But the problem remains the cost and power of FPGAs. Thus, the inevitable solution is a hybrid one.

The hybrid solution: ASIC plus embedded FPGAs – a truly programmable data plane

First let’s revisit the benefits of FPGAs. They offer high throughput, low latency, determinism, adaptability and most importantly, reprogrammability! By embedding FPGA technology into an ASICs, you minimize the cost by 90% and power by 85% of discrete FPGAs. Additionally, with embedded FPGA IP, like Flex Logix EFLX IP, you can implement specifically the amount of programmable logic resources as your design requires. EFLX eFPGA IP can be ported to the fabrication node for which your IC is targeted, which is often more advanced than FPGAs, leading to increased performance and lower power – especially considering EFLX eFPGA performance and power can be maximized by leveraging transistor technology and voltage scaling.

This hybrid solution provides the best balance. It enables packet processing algorithms to evolve and adapt to new conditions. Additionally, it maintains the highest level of performance as these critical decisions can be made at the lowest level, the edge, enabling instantaneous processing at the moment of packet arrival. Immediate telemetry can update routing tables and initiate instantaneous packet forwarding. Moreover, malicious packets can be identified and dealt with before entering the network and causing damaging effects such as taking down a server. Most common of these attacks are Distributed Denial of Service (DDoS) attacks. Smart solutions have evolved that utilize a hybrid approach to tackle this problem. See this solution from DynaNIC that cleverly uses programmable logic to capture, filter, divert and tag all traffic of interest at very high speeds. Moreover, this hybrid solution, already proven on EFLX eFPGA IP, provides the capability to continuously adapt to evolving protocols and malicious threats.

Solutions like this bring to life context awareness to traffic monitoring. While these benefits and implementation in programmable logic have long been deployed in networking applications, many others are starting to catch on. Imagine what other applications this technology can benefit. Consider applications like AI where data can come from various input interfaces – video streams, data from high-speed ADCs and networks.

All of these interfaces can benefit from this technology. In this case, incoming data must be depacketized, conditioned, buffered and monitored for unintended or malicious data. Real-time monitoring of all incoming data can provide many benefits including eliminating invalid or uninteresting data, like no changes in video stream, saving processing bandwidth and power. Or more critically, data signing the authenticity of the data source. Flex Logix EFLX eFPGA IP is the perfect partner for this hybrid solution.

Want to learn more about Flex Logix EFLX IP and security solutions? Contact us at [email protected] to learn more or visit our website https://flex-logix.com.