Experts At The Table: IC Manufacturing Challenges

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future manufacturing challenges with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process interactions at Lam Research. What follows are excerpts of that conversation.

SMD: What are the big challenges facing the semiconductor and fab equipment industries today?
Hebb: One of the major challenges is process control. As the nodes shrink, and especially going to finFETs, the equipment must control the process with more uniformity, repeatability, and in a manufacturable way. Those challenges are not rising exponentially, but they are really getting tougher and tougher. We see requirements for in-situ metrology and direct control on whatever you are doing on the wafer. This is especially challenging for foundries, because they have so many mask sets. The issue of pattern loading also plays into this. You also have the challenge of within-die control uniformity. And then you have the challenge within the wafer and then wafer-to-wafer for many different mask sets. And as you go to 3D structures, this is going to become even tougher.
Dixit: Variation is a big factor in everything. Then, you couple that with what’s going on, and what could be projected, for lithography. The other part is materials. And then look at what went into the finFET. Trying to get these things together and do them in a fashion so that you are not worried about variation across the wafer is a challenge. When you compare gate oxide thicknesses 10 years ago to today, you are now talking about having variances of less than a third of that thickness across 300mm substrates. You are talking about very small numbers. That’s a big challenge. Then you start questioning how quickly can things shrink. Can chipmakers really stay on the physical feature size path? Can the industry move fast enough to the next node? And what will be required in next generation nodes?
Mazure: When you look at a tablet or smartphone, it’s not only the processor that has the latest feature size. The device also consists of memory, RF parts, controllers and image sensors. And then you add more and more functionality to a system. You basically don’t use it as a phone anymore. You use it in other ways like mobile computing. So for me, the challenges are how the ecosystem can contribute to reduce the overall power envelope. It’s all about reducing the power envelope without sacrificing performance. For the customer, the ease-of-use must not be impacted.
Wimplinger: The challenge for us is to understand how all of the technologies tie in together. On one hand, we see 3D happening. But it’s a little bit less clear what role 3D will play in the 450mm transition. Will it happen at the same time? That is, of course, is a question mark. We have to think about this, because we have to put the appropriate resources towards our R&D and equipment development.

SMD: Speaking of 450mm, what are the challenges in terms of moving to the next wafer size?
Hebb: In 450mm, you divide it into economic problems and technical problems. On the technical side, managing the uniformity across the entire wafer is going to be challenging. But the general problem for equipment suppliers is that 450mm obviously diverts R&D dollars. So now, you not only have to develop your equipment for new capabilities and materials, but you also have to develop your tools for the bigger wafer sizes. With all of this, you’re selling less equipment to fewer customers. Nonetheless, we have to get ready for 450mm. 450mm is not going to stop the good companies. Good equipment companies with strong balance sheets will do it and be successful at it.
Dixit: If you look back at the 200mm to 300mm transition, the industry started and stopped the process many times. I think the industry has learned from that. When I look at the big picture, I see some positive changes in the way people operate. The big question for the 450mm transition is how soon and when will it happen?
Wimplinger: For the processes we supply, we think our equipment is fairly scalable. Our concern is where to put those R&D dollars. There are other challenges with 450mm. Although Sematech is trying to put (a 450mm consortium) together, it’s not fully clear who will be playing which role. There are institutes in Europe that have been active like IMEC. There are some in Asia who want to play a role. But there are only so many resources available to work with everyone. The thing we learned is that we have to become more pro-active in the transition. If you’re a little ahead when you are really getting pushed by customers, it’s a little less painful.
Mazure: Our position is more like the IC companies. To make SOI, we need to buy the equipment. In that sense, we’re fully aligned with the equipment roadmap. We have already demonstrated the feasibility of scaling up to 450mm. But we shouldn’t forget to address the other wafer sizes. For example, leading edge in RF is still at 200mm. There is also a lot of power management at 200mm. In automotive, you don’t need 450mm. You are looking at 300mm and mainly 200mm.

SMD: To ensure that 450mm and EUV are on time, Intel, TSMC and Samsung recently invested in ASML. Are we seeing a new business model evolving in the equipment industry, where IC makers invest in fab tool vendors?
Mazure: Only the leading-edge chipmakers are pushing for 450mm. That reduces the market to just a few companies. And that puts incredible pressure on the equipment suppliers. So if leading-edge chipmakers want 450mm to happen at a certain timeline, they have to change the model.
Hebb: Intel’s move to work with ASML is a good sign. The chipmakers are recognizing that they need to kick in some funding. But that’s really the first sign we’ve seen. My gut feeling is that (the investments in ASML) might be a special case because of the cost of the lithography equipment. Leading-edge lithography is set apart just by the sheer capital costs of the equipment. So leading-edge chipmakers must fund some the equipment R&D to secure access to it in the future.