Heterogeneous Redundant Circuit Design Approaches for FPGAs

New research paper titled “Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs” from researchers at Nagasaki University.

Abstract (Partial)

“In this paper, we present and evaluates two heterogeneous redundant circuit design approaches for FPGAs: a resource-level approach and strategy-level approach. The resource-level approach focuses on diversity in FPGA technology mapping. For example, two different implementations for a multiplier, one with look-up tables (LUTs) and the other with digital signal processing (DSP) blocks, can form heterogeneous redundancy. The strategy-level approach makes the use of the optimization options offered by an FPGA design tool, called strategies, as a source of diversity. For example, two different implementations can be derived from the same hardware description with area oriented optimization and performance oriented optimization. With both approaches, heterogeneous implementation variants can be generated from the same hardware description code. For evaluation, we implemented homogeneous and heterogeneous redundant designs for proportional-integral-derivative (PID) control with those approaches and evaluated their error detection capability and reliability with overclock simulation. The resource-level approach showed that heterogeneous redundant designs by the proposed method have a high error detection rate in both RTL and HLS implementations in an application-level circuit. Although the detection rate of the strategy-level approach was not as high as that of the resource-level one, it was shown to have a certain diversification effect.”

Find the technical paper here. Published 2022.

Taichi Saikai, Kotoko Miyata, Taito Manabe, Yuichiro Shibata, Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs, International Journal of Networking and Computing, 2022, Volume 12, Issue 2, Pages 387-405, Released on J-STAGE July 06, 2022, Online ISSN 2185-2847, Print ISSN 2185-2839, https://doi.org/10.15803/ijnc.12.2_387, https://www.jstage.jst.go.jp/article/ijnc/12/2/12_387/_article/-char/en.

Visit Semiconductor Engineering’s Technical Paper library here and discover many more chip industry academic papers.