High-Stakes Litho Game

Developing EUV was only the first step. Selling it to the semiconductor industry comes next.


The commercial introduction of EUV looks all but assured these days. There is enough history to show it works. Uptime and throughput are improving, and systems are shipping today. The question now is how to measure its success.

In the short-term, this is a fairly simple financial exercise for companies like ASML and Zeiss, which have been closely collaborating to get these massive systems out the door and off to customer sites. It likewise will be a straightforward financial exercise for companies like Intel, Samsung, GlobalFoundries and TSMC, which are in dire need of these systems at 10/7nm, particularly for the mask cuts and maybe for patterning metal layers 1 and 2.

The big question, though, is what happens over the next couple of process nodes. For Intel and Samsung, which are IDMs with commercial foundry operations, there is enough captive business to make a case for these investments. GlobalFoundries likewise has an agreement in place to develop server chips for IBM. And for those companies, there is an EUV roadmap in place now to steadily increase the number of wafers per hour and, using high numerical aperture technology, to extend lithography down to 1.5nm and maybe even 1nm.

But for pure-play foundries, which is where the vast majority of chips are manufactured, this is still an expensive gamble. EUV development turned out to be much harder than anyone expected, which is why it has shown up five process nodes after it was expected to be introduced. During that time much has changed. The market for smartphones has flattened. And while server chips are in great demand due to an explosion of data, the volume of chips produced for servers is a fraction of the size of the mobile processor market.

Beyond that, many of the new computing architectures are less reliant on process geometries than on chip architectures. Shrinking a chip to 5nm may not offer improvements in speed or power by itself. IBM, Intel and GlobalFoundries all are looking at multiple paths forward. So are the commercial foundries. TSMC’s biggest customer, Apple, has adopted fan-out wafer-level technology, which means the entire chip doesn’t have to be developed at the latest process node.

In addition, many of the new volume markets for chips—virtual/augmented reality, industrial and regular IoT, autonomous vehicles, and even some cloud operations—do not require the latest process technology. In fact, some of the newer datacenter computing approaches, such as quantum computing, can be built using older-node technology.

Add to that the commercial success of multi-patterning, improvements at older nodes, and new packaging options such as 2.5D and 3D-IC, and the market for EUV looks very different than when a team of scientists embarked on what is unequivocally one of the most complicated pieces of technology ever developed. Rather than the only way forward, even for the most advanced chips it will likely only be one piece of the path forward. And that has a big impact on the economics for EUV in particular, and advanced processes in general.

It’s possible to continue shrinking chips, and it’s likely that digital logic will continue to utilize the latest lithography technology available. But in the future, economics and physics will play a bigger role in the final decision about lithography, architectures and process geometries.

The lithography problem is solved, more or less. Now the question being asked at the bleeding edge is when, where and how often it will get used, and whether it will ever achieve the economies of scale that have made process shrinks inevitable in the past. At 5nm, new gate structures and interconnects will be required, thermal management will become more difficult due to increased dynamic power density, thermal effects will become more problematic, and electron tunneling will require completely different design strategies to ensure signal integrity and overall system reliability.

The bottom line is that lithography is not the sticking point anymore. It’s the market for that lithography, and so far there are no clear answers about how fast that will grow.

Related Stories
Extending EUV Beyond 3nm
Now that EUV is finally shipping, companies are working on extending it much further using anamorphic lenses and high numerical aperture technology.
Moore’s Law: A Status Report
The ability to shrink devices will continue for at least four more nodes as EUV begins to ramp, but it’s just one of a growing number of options.
Why EUV Is So Difficult
One of the most complex technologies ever developed is getting closer to rollout. Here’s why it took so long, and why it still isn’t a sure thing.
Inside Lithography And Masks (Part 2)
Where EUV fits, what problems still remain, and what are the alternatives.

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