How To Extend Litho Scaling

IC mask today is sophisticated and complex. It’s also a work in progress with a lot of unknowns as the industry struggles to increase productivity while reducing risk.

The bulk of the work currently is focused on trying to figure out what would be a practical scheme for patterning lithography that could be used at 10nm and 7nm, said Gandharv Bhatara, Calibre OPC product marketing manager at Mentor Graphics. “Right now, there are three pathways—immersion lithography with multiple patterning, EUV, and DSA (directed self assembly). Within the industry there seems to be a consensus emerging that even though multiple patterning is expensive, right now that’s the viable solution for 10nm given the timing of EUV, so most companies are going to adopt that unless significant strides happen with EUV in the next year or so.”

He said that while DSA always was positioned as an interesting 7nm candidate for contact holes and for fins, it’s a complementary patterning strategy that needs to show a significant value improvement compared with multiple patterning.

There are several options within multiple patterning, as well, including pitch-splitting triple patterning, which will make its advent at 10nm and 7nm, or self-aligned double patterning or self aligned triple patterning, which likely will be used on different layers.

There are limitations to overcome with all of them. George Bailey, technical marketing director at Synopsys, explained that hardware changes are required at each new process node, and in the past hardware would keep pace with the process technology. Over time a gap has emerged, resulting in marginal process windows. “More advanced materials are being deployed, which now creates model problems. Designs are still becoming more compact, which also drives up correction times and complexity. Costs subsequently rise, too.”

One of the big challenges is polygon manipulation without adding complexity and driving up runtime and cost. Work also needs to be done in the modeling space because the lithographic systems are being pushed to their limits, new materials are being added, and there is pressure to do more prediction with models. That increases the complexity of the modeling, as well.

“Over time, about every five years, new materials or new optical effects have to kick in and it’s compounding. So a compact mode, which traditionally could be pure optical and predictive, reasonable, and accurate is becoming less so, and it has to maintain this pace.”

The way Aki Fujimura, CEO of D2S sees it, wafer lithography is really not changing very much. “The story is the same: EUV is coming, we all hope EUV comes at 7nm, but we all have doubts. What that means is that we have to do more multiple patterning.”

On the mask side, however, there are a lot of interesting things going on, he said. “First is the transition to what is now recognized as a simulation-based verification and data preparation from a CAD point of view. Simulation verification preparation has become widely recognized as absolutely required for the leading edge. It hasn’t been too long since the mean and size of a feature you could write on a mask-writing machine was 100nm x 100nm square, and there was a very good reason for that. Below that, what you actually get on the mask is significantly different from the e-beam projection that was cast onto the mask, and a lot of inaccuracies started to happen.”

Getting to 60nm and below features is where the problems really begin. “You need 50 or even 40nm features on the mask for them to be accurate and for them to be accurate every time it is printed,” Fujimara said. “Inaccurate could mean you want 40nm but you get 35nm. But unreliably inaccurate means sometimes you get 30, sometimes you get 42, sometimes you get nothing — and that’s the kind that you can’t have. If it was reliably inaccurate, there are ways to correct for it, but if it is unreliable, there is nothing you can do. Wafer simulation that was done during OPC was counting on a mask shape to be something and if you can’t count on it to be that every time, then you’re not going to be able to get what you want on a wafer. This unreliability kills any mask.”

But all of these small shape and complex shapes need to be written on the mask, which requires simulation-based processing. That opens the door to overlap shots and other types of manipulations while still hitting the desired target.

“Probably the biggest thing that’s happening in the mask lithography world is the prospect of multi-beam machines for the 7nm node,” Fujimura said. “This is really significant because multi-beam machines are constant-light-time machines, so no matter how complex the shape you want on the mask, the amount of time if takes to write it is the same. You couldn’t do it before because it would cost too much write time, but you will be able to do it once these multi beam machines become available for production masks.”

Tool readiness
As far as tool readiness is concerned from a computational lithography perspective, Mentor’s Bhatara said one thing that’s become critical—especially in the area of multiple patterning—is that the entire flow must be considered. That includes everything from design enablement (decomposition) to how you do fill, to how you do OPC.

“Reliability and yield are a big deal,” he said. “How do you come up with solutions that allow you to squeeze out that extra nanometer that you need at 10nm and 7nm? How do you ensure that you don’t have any hotspots because process margins are getting extremely tight?”

Work is still underway on the computational lithography front to ensure that people are able to get their foundry metrics with much of the work done in a co-development partnership model, especially given that below 20nm things are very specific. In Mentor’s case, the company has increased its engineering headcount by about 50% in the past two years.

“All of this work is creating a lot more models and OPC layers, while development complexity goes through the roof. Run-times are out of control, but the engineering resources in most companies are staying the same. They still have the same number of engineers that have an expectation of meeting the same schedules under the same constraints. This has placed a lot of responsibility on tool providers,” Bhatara added.

Manoj Chacko, product management director at Cadence, believes the most significant advancement to IC mask lithography in the recent years has been the enablement from material and software enhancements. And it is this contribution that is the key enabler to today’s advanced node manufacturing.

“The demise of optical lithography has been predicted by many over the last two decades, and we are continuing to enter new frontiers,” Chacko said. “One of the critical contributors that is enabling this advanced-node march is software-based computational lithography technology. There is a whole array of technology names and acronyms that have emerged to simply satisfy the economic viability of sustaining Moore’s law. A few of the prominent technology names we hear or have heard are multi-patterning (double, triple, or quadruple), multiple exposures, source and mask optimization, pixelated masks, inverse lithography, and so on.”

With the delay in EUV—and possibly even with EUV—more advanced computational lithography will be needed. “If history has to repeat itself, I’d say more advancements will come to enable lithography scaling and the decision to adopt the next generation lithography technology will be influenced by economic factors rather than technical factors,” Chacko concluded.