How We’ll Get There from Here

The symbiotic relationship between systems designers and the semiconductor and EDA ecosystem is what keeps the industry nimble.

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The electronics industry is like a battleship with remarkable handling properties.

I thought about it this week sitting at an industry event a day after stumbling across Neptune—the technology project, not the god. Those two experiences forced me to rethink some fundamental assumptions about system design and how the ecosystem responds to change.

If you’ve not heard of Neptune, it’s an Indiegogo project that’s raised nearly $1 million, almost 10 times its goal. It’s a wearable/mobile play that turns the paradigm on its head. Today, the hub for most wearables is the smart phone. Your wearable watch captures and computes data, but the alpha dog in the relationship is the smart phone (or even the laptop).

In the Neptune architecture, the hub is the watch. A pocket device serves as your “phone” but is effectively a screen that interfaces with the hub, which runs Android Lollipop. You also can buy a “dumb” tablet for that type of experience and a wireless keyboard to have a PC experience.

What makes this thing tick is that the hub uses WiGig (7 Gb/s) to stream data to all the ancillary devices, almost latency free. And battery life is optimized across all devices—from a 1000 mAh battery in the watch to 2800 in the pocket screen to 7000 mAh in the tablet screen. (By comparison, the iPhone 6 battery is 1800 mAh).

This type of radical rethinking of design and power considerations has been having an impact all up and down the food chain.

Nowhere was this more evident this week than at the annual TSMC Technology Symposium in San Jose. Co-CEO Mark Liu always offers an impressive technology and services roadmap at this event, but this year he seemed even more forceful in his statements. This no doubt stemmed from increasing competition the No. 1 foundry is sensing as the likes of Global Foundries, UMC, and Intel all drive for more of the action, especially in mobile designs.

Liu’s headline announcement was TSMC’s 16FinFETC (16FFC) process, an ultra-low-power “compact version” of the established 16FF+ technology. 16FFC cuts power consumption by 50% compared with 16FF+ and offers a nominal voltage of 0.55V—a nod toward power-conscious wearables designs. Version 1.0 design collateral will be available in the first quarter of 2016 with product tapeouts expected in the second half of that year.

“Its cost and power reduction advantages can help you meet your mainstream market demands, including mid- to low-end smart phones; consumer products and wearables and such,” Liu told an audience of more than 1,000 electronics industry executives.

Power and integration potential weaved their way through presentations all day at the San Jose Convention Center. Liu also updated the crowd on 16FF+, which consumes 50% less total power than the TSMC’s own 20nm SoC process. Toward the end of last year, TSMC announced its ultra-low power platform, rolling out 55 ULP, 40 ULP and 28 ULP.

For the emerging 10nm node, TSMC has demonstrated yield on a fully functional 256 Mbit SRAM. The logic density is 2.1X better than the company’s 16nm node, Liu added. Risk production is scheduled for Q4 2015 with production volumes following a year later, he said.

These are both reactions to and enablers of new thinking going on across the globe at the system level. The technology hurdles for everyone are non-trivial. SemiEngineering’s Mark Lapedus offered an excellent overview, saying chipmakers see a path to 5nm (2019 time frame) using traditional CMOS. Then what?

Before the TSMC Technology Symposium I chatted with Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division, and asked him what comes after 10nm. He was bullish on Moore’s Law future and cagey on how we get well past 10nm.

“I don’t want to make any comment on a specific technology node number but we’re working on future platform technology development,” he said. “We have a team working on the next generation after 10nm. Those technologies are going to be offered in the 2017 to 2019 period. We don’t anticipate Moore’s Law is going to slow down anytime soon.”

Then I asked about some industry assessments that finFET is a two- or perhaps three-node phenomenon.

He said:
“The next big challenge has to do with continuing the ability to do patterning based on existing light sources. At 10nm, no one is dependent on EUV. We’ve set up our 10nm technology so that when and if EUV comes on line we can take advantage of it. The technology itself is very complex. We need to get to a point where there’s sufficient wattage and uptime so there are significant wafer volumes.”

At the symposium, TSMC R&D Vice President YJ Mii noted that the company’s work with ASML R&D on EUV has pushed the power source to 90W as the fourth quarter of 2014. They expect to achieve 150W this year, he said.

It’s this type of relentless progress with an increasing emphasis on power that’s helped foster projects like Neptune.

And it’s the symbiosis between systems designers and the semiconductor and EDA ecosystem that seems keep this battleship of an industry remarkably nimble.