Imec’s Plan For Continued Scaling

At IEDM in December, the opening keynote (technically “Plenary 1”) was by Sri Samevadam of Imec. His presentation was titled “Towards Atomic Channels and Deconstructed Chips.” He presented Imec’s view of the future of semiconductors going forward, both Moore’s Law (scaling) and More than Moore (advanced packaging and multiple die). It is always interesting to hear Imec’s view of the world since it is a sort of Switzerland of the industry. All major semiconductor companies are engaged with Imec in pre-competitive research. There are over 500 “guest” engineers from these companies who work onsite at Imec.

This is really important since there needs to be a reasonable level of agreement on the direction to go. Although semiconductor companies differ in details of their processes, there has to be basic agreement on what equipment and materials are required since the whole ecosystem needs to come along too. A good example of this has been the development of EUV. Imec was especially well suited to be involved in this since ASML, the only company to supply EUV steppers, is “up the road” in the Netherlands, just a one-hour drive away. The three leading-edge semiconductor companies were all going to get basically the same equipment and Imec, who had an EUV stepper early on, was the place to work out what it was capable of. To learn more about Imec, see my post If It’s Tuesday This Must Be Belgium. My First Visit to Imec.

Sri started with an overview of scaling in the past. It’s a story I’m sure you know: the end of Denard scaling when the voltage could no longer be lowered due to short-channel effects, copper interconnect, strained silicon, HKMG, FinFET, and in the near future, GAA nanosheets.

Next, he moved to the future and the EUV roadmap in particular. For 3nm and beyond, it will be necessary to use multiple-patterning, either SADP or SALELE (this stands for self-aligned litho-etch-litho-etch, but I don’t know how the alignment is achieved unlike SADP that uses a mandrel). The hope is high numerical aperture (NA) EUV, which should get us back to single patterning, but that is at least a few years out. Sri’s cost estimates (assuming high-NA EUV is 1.5X the cost of today’s EUV, (so about $150+M per stepper) are that high-NA will be 5% lower during early adoption and 14% lower in full production.

Moving on to logic scaling, Sri had the above diagram. Obviously, as you go across, the process goes from 3nm to 1nm. Key requirements are buried power rail (BPR) instead of putting the main power distribution in interconnect. Transistors move to gate all around nanosheets (for higher drive, lower leakage). To get the number of standard cell tracks below 5 requires forksheets, moving the P and N transistors closer, and to get down to 4 tracks requires CFET (complementary FET) where the P and N transistors are vertically stacked one above the other. For 1nm and beyond, there will be a need to switch to two-dimensional channel materials. Buried power rail (BPR) also opens up the possibility of backside power distribution, and eventually other features on the backside such as decaps.

CFETs allow the n-transistor to be stacked on top of the p-transistor, saving a lot of area at the cost of process complexity. However, there remain many technical challenges to manufacture, such as the common gate and the thermal issues that often accompany 3D structures.

The next generation is some sort of 2D channel material such as MoS₂ (molybdenum disulfide) but currently, demonstration vehicles are an order of magnitude worse than state-of-the-art silicon-based channels. But there is nothing other than 2D materials on the horizon, so further investigation is essential.

For interconnect, today we have dual-damascene copper, but to address via resistance we’ll need a hybrid solution with a second metal like ruthenium (and a thinner barrier). For further advancement, we need a semi-damascene process, but copper can’t easily be etched so it will need to be some other material. Eventually, we’ll need completely new materials.

SRAM scaling is also under pressure and has slowed recently. But SRAM also benefits for many of the device innovation I already mentioned, such as CFETs or BPR.

Next up, More than Moore, 3D SoC design. One big challenge today is that EDA tools to do this do not yet exist, except for the most simple cases such as partitioning memory and logic. Sticking die like this presupposes high-density 3D interconnect.

Sri feels that EDA advancement needs to accelerate, eventually delivering a full 3D-aware design environment, as shown in the diagram above.

Summary

Sri feels we have a research agenda for the next ten years, especially in the areas of 2D materials. Also, for 3D chips, more research is needed on silicon structures such as backside power distribution, and also a full design suite of EDA tools for full 3D design.