Improving Patterning Yield At The 5nm Semiconductor Node

Engineering decisions are always data-driven. As scientists, we only believe in facts and not in intuition or feelings.

At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconductor manufacturing can provide facts that engineers can use to make immediate and accurate decisions, such as how they might correct any excursion or yield drift. Data exists, so life is (kind of…) easy!

Looking at the development (or more importantly, research) stage in this field, we notice that there is an important gap in data and facts. Important decisions need to be made at the R&D stage, for instance, defining a Process of Record process flow. These decisions need to be made fast to stay in the Moore’s law race. Any wrong decision will be very costly, if you consider the time and cost associated with experimental wafer starts in a fab. This is exactly where data-driven decisions are needed.  Unfortunately, due to the innovative nature of the R&D process and lack of manufacturing information for any new technology, very little statistical data is available. This lack of data at the R&D stage can be ameliorated, using virtual fabrication technologies available in Coventor’s SEMulator3D software.

At the 2018 SPIE Advanced Lithography Conference, I presented a study about using SEMulator3D to assess different process options. We reviewed Metal 2 (M2) Blocks and Metal 2 – to – Metal 1 Via for the imec iN5 node (imec 5nm node, foundry 3nm node)^[1].

Looking at the M2 tight pitch associated with the iN5 node, block/via printing and alignment become a key challenge in addition to M2 line patterning (using Self-Aligned Quadruple Patterning – SAQP). Imec has recently proposed new process integration options for self-aligning the patterning of the blocks^[2] and the via^[3], called Self-Aligned Blocks (SAB) and Fully Self-Aligned Via (FSAV), respectively. These integration options were first modeled using SEMulator3D virtual fabrication. Once these models were developed, we used the SEMulator3D Analytics feature to generate Virtual DOEs (Design of Experiment). For each of the four process flow options (standard Block and standard Via, Self-Aligned Block and standard Via, standard Block and Fully-Self Aligned Via, Self-Aligned Block and Fully-Self Aligned Via), we launched 100 runs screening a total 15 different lithography process parameters (overlay, bias, Line Edge Roughness for M2 line, blocks and Via lithography steps). A Monte-Carlo distribution was produced for each of those process parameters and three cases were considered: a default 1-sigma scenario (corresponding to imec standard deviation capabilities) and alternative 2- and 3-sigma scenarios where standard deviations are multiplied by 2 or 3 to simulate extreme process control variations. For each of those 400 simulation runs (4 process flow options x 100 runs per option), we used SEMulator3D virtual metrology to inspect the electrical connections of each M2 line and each M2-to-M1 line connection using specific success criteria (Figure 1).

Figure 1: Resistance extraction between M1 and M2 lines and Figure of Merit matrix (1: connected, 0: isolated)

Based upon our metrology results, we determined the patterning yield of each process flow option (Figure 2) and determined that SAB offers a consistent patterning yield boost for > 1-sigma cases whereas FSAV does not have any impact.

Figure 2: Patterning Yield vs. Process Option

The benefits of FSAV, which are reliability and not yield related, are also discussed in a paper written about our study. Finally, we also determined that for the default 1-sigma case, process control was tight enough to guarantee high patterning yield and that self-aligned options would only help avoid excursions but did not further enhance yield.

If you would like to learn more about this study, please click here to receive a complimentary copy of the full paper describing these results.

References

[1] Benjamin Vincent, Joern-Holger Franke, Aurelie Juncker, Frederic Lazzarinob, Gayle Murdochb, Sandip Halderb, Joseph Ervin., “Self-Aligned Block and Fully Self-Aligned Via for iN5 Metal 2 Self-Aligned Quadruple Patterning”, SPIE Advanced Lithography conference (unpublished, 2018, DOI: https://doi.org/10.1117/12.2298761)

[2] Lazzarino, F., Mohanty, N., Feurprier, Y., Huli, L. et al, “Self-Aligned Block technology: a step toward further scaling,” Proc. SPIE 10149, 1014908 (2017)

[3] Murdoch, G., Boemmels, J., Wilson, C.J. et al, “Feasibility study of fully self-aligned Vias for 5nm node BEOL”, Interconnect Technology conference (IITC), 2017, IEEE International, pp. 2380-6338 (2017).