Improving Yield With Machine Learning

Machine learning is becoming increasingly valuable in semiconductor manufacturing, where it is being used to improve yield and throughput.

This is especially important in process control, where data sets are noisy. Neural networks can identify patterns that exceed human capability, or perform classification faster. Consequently, they are being deployed across a variety of manufacturing processes to spot defects and determine whether they will affect the functioning of a device over its anticipated lifetime.

“A lot of AI stuff is starting to happen now, where customers are identifying the most relevant measurements,” said Subodh Kulkarni, president and CEO of CyberOptics. “We extract the outliers, and the integration happens one level above, leading to new levels of yield improvement.”

Machine learning has been in use in the inspection arena for the longest of any manufacturing process, and it is being incorporated into new tools. Algorithms can isolate defect signatures or patterns that are unknown to the yield engineer.

“KLA’s broadband optical inspection systems have on-tool binning technology that uses defect attributes to separate detected events into different defect types and nuisance defects using machine learning,” said Satya Kurada, vice president of marketing at KLA.

Defects identified on optical tools that require additional classification are typically reviewed on e-beam inspection systems. “Fab engineers use the defect information to optimize the production line,” Kurada said. “The end result should be more good die making it to end of line, where probe takes place.”

Like the human brain, deep learning (DL) recognizes patterns and uses that information to judge incoming data automatically. Using a cascade of multilayer, nonlinear processing units for feature extraction and transformation, each layer in a neural network uses the output of the previous layer as input for the next layer. In defect inspection, DL- or ML-based algorithms reduce the burden of manual classification and reduce time to result.

The automated nature of the networks also makes them attractive. “Because a deep learning model instantly updates itself, there’s less maintenance,” said Mike McIntyre, director of software product management at Onto Innovation. “But you also can’t do the diagnostic. That’s the thrill of this new modeling. I have less effort for maintenance than I would with my old machine logic models, where I would constantly have to tweak a slope, or an intercept, or a variable to make sure it remains consistent. So it’s important to trust but verify with different datasets. Also, these software solutions are not ‘set it and forget it.’ Our True ADC is a process tool, just like any other in the factory.”

Streamlining ADC
Automated defect classification (ADC) using images from optical microscopes or SEMs, or both, is the most widely used approach for defect analysis in fabs. Many state-of-the-art ADC methods are based on convolutional neural networks (CNNs). However, typical CNNs cannot achieve the high classification accuracy needed in semiconductors, and they are expensive.

Synopsys engineers recently found that a decision tree deep learning method can classify 98% of defects and features at 60X faster retraining time than traditional CNNs. The decision tree utilizes 8 CNNs and ResNet to automatically classify 12 defect types with images from SEM and optical tools (see figure 1). They presented their results at the SEMI’s recent Advanced Semiconductor Manufacturing Conference (ASMC).[1]

Fig. 1: A dozen defects types were classified using a decision-tree NN, incorporating multiple convolutional neural networks to achieve higher defect classification accuracy. Source: Synopsys/IEEE ASMC

“We chose ResNet because it has been widely used in multi-classification problems, such as classifying satellite images with the best performance among AlexNet, VGGNet, and GoogLeNet,” said Zhixing Li, senior research and development engineer at Synopsys. “ResNet was also the first ImageNet winner with better performance than human vision.”

Synopsys noted that its neural network is smaller than any single CNN and is trained more quickly. Its self-learning mechanism works by reporting images as “unknown” if classification confidence is below the required threshold. The engineers then inspected the 2% unknown defects, labeled them, and retrained that particular DNN.

Fig. 2: The decision tree neural network reduces computational resources because individual branches can be retrained instead of retraining the whole neural network. Source: Synopsys/IEEE ASMC

“This is possible since the decision tree of DNNs permits the retraining of one DNNs instead of the entire system,” said Li, explaining that the decision tree was created with domain knowledge of the defects. Those defects were grouped into classes and super-classes based on common physical features, resulting in a 4-level decision tree. Run time for the program was 98 minutes.

One of the reasons neural networks are so useful is that semiconductor processes are now so complex. Take 3D NAND structures, for example. Both Macronix and KLA recently showed the benefits of applying deep learning to 3D NAND processes. The Macronix study showed machine learning enabled faster ramp of a deep trench etch process with excellent across-wafer uniformity. KLA engineers showed that applying deep learning to an e-beam defect inspection tool helps identify deep buried defects of interest in 96-layer trenches.

Fig. 3: Process flow for deep slit trench etch. Source: Macronix, IEEE ASMC

Deep trench etch optimization
Macronix engineers showed how machine learning can expedite new etch process development in 3D NAND devices. Two parameters are particularly important in optimizing the deep trench slit etch — bottom CD and depth of polysilicon etch recess, also known as the etch stop (see figure 3). “Too small of bottom CD patterning will cause wordline-to-wordline shorts, and punch-through of the first poly layer will lead to pattern structure collapse,” said Yu-Fan Chang, engineer at Macronix.

The Macronix team determined that a traditional domain knowledge method did not meet across-wafer uniformity needs, so they turned to a machine learning model to rapidly optimize the etch BCD and poly recess at wafer center, middle, and edge, presenting their results at SEMI’s ASMC.[2]

People tend to think of neural networks as requiring very large data sets, but that’s not always necessary. “Even if the database size is limited, we can still apply it to reduce the turnaround time of etch development and work out a clear tuning trend through a series of virtual profile prediction and validation during NN modeling,” Chang said.

In the deep trench etch process, the target bottom CD is >150nm, and the poly recess target is <65nm. The 7-step model includes:
1. Data collection — SEM cross-sections at center, middle, edge;
2. Data mining — determining variable influence (O2 flow, etch time, power, etc.) on BCD, poly recess;
3. Model set-up;
4. Model selection;
5. Model check — done by test data, if yes, 6, if not, 3;
6. Prediction — ideal bottom CD and poly recess,
7. Accuracy check — using actual etch profile

Steps 2-7 are repeated until target results are delivered. In neural networks, the variable outputs (neurons) provide the input to the next steps. In this particular case, 12 etch variables feed 6 activation functions in the first hidden layer, and 8 activation functions in the second hidden layer, comprised of TanH, linear and gaussian functions. The 4-layer neural network simultaneously predicts center, middle, and edge BCD, and poly recess values (see figure 4).

Fig. 4: The four-layer, feed forward neural network model predicts bottom CD and poly recess at center, C, middle, M, and edge, E, of the wafer simultaneously. Source: Macronix, IEEE ASMC

The group validated the model by comparing actual data SEMs (see figure 5) using known data, and compared the result with that predicted by the model. Model accuracy was >92%. Machine learning successfully identified the ideal process conditions that yield the desired BCD and poly recess values across the wafer with good correlation (R2 = 0.78-1).

Fig. 5: The final deep trench etch process, which was tuned quickly using a 4-layer neural network. Source: Macronix, IEEE ASMC

Classifying Deep Defects in 3D NAND
KLA engineers, led by Cheng Hung Wu, optimized the use of a high landing energy e-beam inspection tool to capture defects buried as deep as 6µm in a 96-layer ONON stacked structure following deep trench etch.[3] The e-beam tool can detect defects that optical inspectors cannot, but only if operated with high landing energy to penetrate deep structures. With this process, KLA was looking to develop an automated detection and classification system for deep trench defects (see figure 6).

Fig. 6: This deep learning model detects and classifies defects with 90% accuracy. Source: KLA, IEEE ASMC

Most defects in the vertical channel inspection are caused by channel under-etch or residual tungsten in the channel (a sacrificial film). The analysis showed a landing energy of 30KeV was ideal for detecting and classifying defects as deep as 6µm in 100nm features. The training and verification runs used 25 defects among 9 vertical channel rows on 4 wafers, revealing 9 defect classes. Verification using FIB cross-section and SEM imaging showed a nuisance rate of 2%.

“This indicates the DL-model is good for finding DOI types with noise filtered out. Nuisance defects are vertical-channel-hole diameter variations, usually smaller than normal ones,” said KLA’s Wu. He noted that manual inspection takes 20 to 30 minutes, while the DL model performs real-time ADC during job runs.

SMT die attach optimization
A memory manufacturer required a more sensitive inspection method for SMT corner underfill, which was being performed using automatic optical inspection with a blob analysis algorithm. The inconsistency of results caused them to turn to a deep learning inspection method to precisely determine the length of epoxy underfill on each device corner.

CyberOptics engineers developed the deep learning algorithm for corner fill inspection that optimized the task of object classification, detection, and transfer learning of the length of the corner fill.[4] “The neural network needs to be deep enough to learn the complicated nature of the problem, but if it’s too deep, it’s difficult to change,” said said Charlie Zhu, vice president of R&D at CyberOptics. “So we need to design the architecture very carefully.”

Fig. 7: Four-side inspection of device underfill quality. Source: CyberOptics

Side cameras on the MRS tool enable four-corner inspection without moving the substrate (see figure 7). The data can be communicated via SQ software, enabling training of the model on one end while the customer runs interference on the other end. Zhu added that the new model training can take several days to a week.

CyberOptics’ Kulkarni said that machine learning and training for specific production applications is likely to be needed more as the complexity of semiconductor packaging increases.

Conclusion
Machine learning algorithms are an important new tool in the engineer’s toolbox, especially for defect classification or bringing new processes to maturity faster. But it’s important to note that these are complex solutions, which are not necessarily required for every problem.

“We’ve got some very, very good solutions with a long track record of 2X and 3X Cpk improvements, but customers want the machine learning solution – even when other proven methods do a fine job,” said Onto’s McIntyre. “Yes, this is another good tool in the toolbox. Engineers will continue to apply machine learning and deep learning, seeing where it can take them in terms of yield improvements and process control, but they are just one tool in the toolbox.”

References
[1] Z. Li, Z. Wang and W. Shi, “Automatic Wafer Defect Classification Based on Decision Tree of Deep Neural Network,” IEEE ASMC, May 2022.
[1] Y.F. Chang, et. al., “Machine Learning Assists on High Aspect Ratio Slit Trench Etching in 3D NAND,” IEEE Advanced Semiconductor Manufacturing Conference (ASMC), May 2022.
[3] C.H. Wu, et.al., “3D NAND Vertical Channel Defect Inspection and Classification Solution on a DL-based E-beam System,” IEEE ASMC, May 2022.
[4] Case Study: Deep Learning for Corner Fill Inspection and Metrology on Integrated Circuits,” Semiconductor Engineering, Dec. 2021, https://semiengineering.com/case-study-deep-learning-for-corner-fill-inspection-and-metrology-on-integrated-circuits/

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