Next Channel Materials?

Chipmakers are making a giant leap from planar transistors to finFETs. Initially, Intel moved into finFET production at 22nm and is now ramping up its second-generation finFETs at 14nm. And the other foundries will enter the finFET fray at 16nm/14nm.

So what’s next? Chipmakers will likely extend the finFET architecture to both 10nm and 7nm, but that by itself may not provide enough of a performance boost. So to help enable faster chips, the industry must address one critical piece of the overall finFET puzzle—the channel materials.

In fact, chipmakers are currently revising their channel-materials efforts amid a multitude of challenges in the arena. For some time, the industry has been searching for an alternative material to replace silicon in the channel. In the channel alone, silicon could run out of steam at 7nm.

Originally, chipmakers were looking at two material types, germanium (Ge) and III-V, for the channel at 7nm. Ge and III-V could provide a mobility boost, which refers to how fast the electrons can move in the channel. But Ge and III-V are more complex than previously thought and may not be ready for 7nm.

Instead, the industry is leaning toward a more evolutionary approach, with silicon-germanium (SiGe) for PFET and tensile silicon for NFET. Ge and III-V are still in the running, if the industry can make a breakthrough in this area.

Still, chipmakers face some tough decisions. First, they must decide when to migrate to new channel materials. The most obvious choice is 7nm, but some may get a head start and shoot for 10nm. Second, IC vendors must find the right blend of materials. And finally, they must choose between one of five different ways to integrate these materials in the fab. The five contenders are blanket epitaxy, selective epitaxy, wafer bonding, condensation, and melt/re-growth.

The leading candidates are blanket and selective epitaxy, which use traditional epi tools to grow monocrystalline films on a structure. “Both approaches are suitable,” said Ivo Raaijmakers, chief technology officer at ASM International, “but the verdict is still out.”

Indeed, epitaxy is sometimes a slow and complex process, prompting the industry to take a look at the alternative methods. “The other approaches might be more cost effective, but they are not ready yet,” said Reza Arghavani, a fellow at LAM Research.

Jumping in the channel
For some time, the channel has been a hot topic. The channel is a conductive region that connects the source and drain in a device. When a MOSFET transistor turns on, the gate capacitor applies an electric field to the channel, creating an inversion layer. This allows minority carriers (holes in PFETs, electrons in NFETs) to flow between the source and the drain.

The big change in the channel took place at 90nm, when the industry introduced strain engineering in the region. Using an epitaxial process, chipmakers integrated SiGe stressors, or distortions in the crystal lattice, in PMOS transistors. This, in turn, boosted hole mobility and drive current.

Using the same epi process, chipmakers are moving towards strain engineering for the NMOS starting at 20nm. The NMOS transistors require a tensile strain, enabling a boost in drive current.

Still, today’s strained-silicon technology is under stress. “The challenge is clear. Can we still get improvements from silicon? Silicon needs more stress, particularly for NMOS. PMOS is actually hitting the limit of the maximum stress that the silicon can tolerate,” said Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries.

So, chipmakers may need to make a materials change in the channels at 10nm or 7nm. At one time, the leading candidate was Ge for PMOS and indium-gallium-arsenide (InGaAs) for NMOS. Ge has an electron mobility of 3,900cm-square-over-Vs, compared to 1,500cm-square-over-Vs for silicon. InGaAs has an electron mobility of 40,000cm-square-over-Vs.

Ge and III-V are fast but difficult to implement. “Growing InGaAs on silicon is challenging. The lattice mismatch is the biggest hurdle with III-V materials,” Banna said. “You can do germanium, but it’s too radical of a step. The challenge is to have a good oxide on germanium.”

Now, the industry is looking at a simpler approach. Chipmakers will likely use SiGe for PMOS at 10nm or 7nm, depending on the company and requirements. For NMOS, the industry may stick with tensile silicon, although a Ge mix could be in the running. “In terms of silicon germanium, it already has a production track record,” said Adam Brand, senior director of the transistor technology group at Applied Materials. “So, the group IV family is going to be the focus area for the different channel materials in the next few nodes. There are still a lot of problems to be ironed out.”

For example, chipmakers must find the right mix of silicon and Ge, which creates the SiGe compound for PMOS. Sematech, for example, has shown good results with a SiGe-based PFET that consists of 75% of silicon and 25% of Ge.

But it’s not as simple as finding the right ratio. To start with, Ge has a 4% lattice mismatch with silicon. In one example, a chipmaker could have a SiGe channel, which consists of a miniscule amount of Ge. This mix might be easier to integrate in the fab, but it could also provide only a tiny boost in performance.

In that case, chipmakers may need to increase the Ge content in the SiGe mix to boost carrier mobility. But this may also add more complexity to the process flow. On top of that, chipmakers may also need to consider increasing the fin height of the finFET, which could boost the drive current in the device. “It’s a tradeoff between the materials intrinsic strength and the fin height,” said GlobalFoundries’ Banna.

The right flow
The next step is to find the right fab flow to integrate the materials. There are two main approaches—blanket and selective epi. The blanket approach calls for the epi materials to be grown everywhere on the surface. In selective, the epi materials are only grown on a select part of the surface.

Both methods use epi tools, which are reliable but slow. In Ge channel materials applications, the throughputs of the epi tools are roughly 10 to 15 wafers an hour, according to experts. “The reason why epi tools run slower is because you have to get to lower temperatures in order to get the growth quality. It’s not an equipment problem. We are trying to make extremely precise crystals and crystals take time to grow,” said Applied’s Brand.

Both blanket and selective epi are viable for advanced channel applications, but some prefer one approach over the other. “If you are looking at strain material like SiGe at 30%, it will be most likely a blanket deposition. That’s the easiest and most manufacturable solution out there,” Brand said.

Selective epi will remain the key process step for source/drain and strain-engineering applications. But it’s unclear if selective epi will prevail for advanced channel applications. “Selective epi is good if you are looking at the replacement trench approach,” Brand said. “But that is actually one of the more difficult technologies.”

The blanket approach has some drawbacks, however. With blanket epi, a chipmaker may end up depositing materials on unwanted regions. In that case, the IC vendor must etch away those materials. All told, blanket epi may have more process steps, possibly making it more expensive.

For that reason, selective epi is also viable. Imec, for one, has developed such a process for III-V and other materials. “In the selective method, the implementation matches the finFET architecture. You mix and match materials with other types of materials. That’s why we believe the selective process is the easiest to implement,” said Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. “But when you put these materials into the geometries, they interact with the geometries and then defects form. So it’s more challenging in terms of defectivity.”

Given the issues with epi, the industry is looking at three other methods—wafer bonding; condensation; and melt/regrowth. “The lead approach is still traditional epi growth. That’s within our reach,” said Lam’s Arghavani. “All of the alternative approaches are being proposed, because people are worried about cost.”

Wafer bonding involves a two-step process. First, a chipmaker patterns Ge layers on top of a donor wafer. That wafer is flipped and the Ge donor wafer is bonded to the main wafer. Then, the donor wafer is removed in an epitaxial lift-off process.

The big challenge is to fabricate a donor wafer with low defects. Any defects will transfer to the device. Wafer bonding is a good technology for chip assembly, but it’s untested for front-end materials integration. “Today, we are not doing that,” Arghavani said. “This is not the lead approach.”

The condensation method is geared for PMOS and silicon-on-insulator (SOI) substrates. In the lab, IBM and GlobalFoundries devised a strained Ge-on-insulator process in a 3.3nm finFET. In the condensation flow, an epi tool grows a strain SiGe layer on SOI. Then, the wafer undergoes a Ge condensation process at a given temperature, creating an oxide layer on the top of the device. Then, the device undergoes another condensation process.

And in another method, some have demonstrated the selective growth of Ge epitaxial layers in channels on patterned silicon substrates. This is done using a Ge melt and regrowth process during a millisecond laser anneal.

“Regarding germanium condensation, it’s very promising,” Imec’s Thean said. “We’ve tried the melt and regrowth option. The issue is that germanium doesn’t like heat. If there are tiny structures, where you melt it and then re-grow it, the problem is that they move everywhere. So that is an issue.”

All told, the industry is still weighing a number of materials and tool options at 10nm and 7nm. SiGe and some form of epi appear to be the early winners, but there are several unknowns. “There are a lot of things in the works,” Applied’s Brand said. “The device makers are still looking at multiple options in parallel.”