Integrating FPGA: Comparison Of Chiplets Vs. eFPGA

Two ways for an SoC to take advantage of FPGA flexibility and the applications where each shine.


FPGA is widely popular in systems for its flexibility and adaptability. Increasingly, it is being used in high volume applications. As volumes grow, system designers can consider integration of the FPGA into an SoC to reduce cost, reduce power and/or improve performance.

There are two options for integrating FPGA into an SoC:

  • FPGA chiplets, which replace the power hungry SERDES/PHYs with special die-to-die interconnects to communicate with the companion SoC die
  • eFPGA, which is an IP block that is put on the SoC die

How do these alternatives compare? As we’ll see, it depends on the application and the priorities.

Use cases for integrating FPGA into an SoC
There are several applications where integrating an FPGA has advantages:

  1. In an existing system where an FPGA is paired with an SoC, for example a Smart NIC or Microsoft Azure
  2. To provide flexibility for an SoC to change algorithms and/or protocols as standards change or for the needs of different customers
  3. Acceleration for SoCs where critical workloads run faster on parallel FPGA than processors
  4. To provide programmable state machines in architectures that have arrays of compute elements, such as many new AI accelerators

FPGA chiplets
New versions of Intel (nee Altera) and Xilinx FPGAs are actually made up of chiplets.

The power-hungry high speed SERDES are the connectivity tiles in this diagram. EMIB is Intel’s proprietary wide-bus high bandwidth chip-to-chip interconnect.

The FPGA chiplet in the middle is primarily digital logic. Intel and Xilinx will, for certain customers at least, provide die for integration into SoCs using interposers, see an example below:

In this way, an SoC and an FPGA chiplet can be co-packaged with a wide, high speed bus connecting them.

Pros and cons of FPGA chiplets vs. eFPGA
An application where a large FPGA is being integrated with an SoC where the coupling between the two is a single bus lends itself well to the above chiplet approach. Examples include a Smart Network Interface Controller or a large accelerator.

The disadvantages of the chiplet approach are:

  • the high cost of multi-die packaging using substrates
  • the need to use a specialized die-to-die interface on your SoC that you may not be familiar with or are unable to get from your PHY IP supplier
  • the smallest FPGA chiplets available still have a large number of LUTs which may exceed the requirement

The applications where eFPGA may be a better solution are:

  • those where the die cost of eFPGA+SoC is lower than the cost of the interposer and chiplet+SoC
  • those where the amount of eFPGA required is 10s of thousands of LUTs: such small chiplets are not available and the die area required on the SoC is minimal
  • architectures where eFPGA is distributed across the die in many locations, such as in an array of compute elements where the eFPGA is a programmable state machine for local control of high speed compute blocks: chiplets are really only practical for a single large block of FPGA

FPGA is increasingly appearing in high volume applications so we will see increased use of chiplets and eFPGA to keep down cost and power, and to increase performance. Both options have advantages in certain applications and we will see both of them co-existing in the market place with rapidly increasing use of both.

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