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Is This The Year Of The Chiplet?

Why this approach will have deep and lasting effects for the entire semiconductor industry.

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Customizing chips by choosing pre-characterized — and most likely hardened IP — from a menu of options appears to be gaining ground. It’s rare to go to a conference these days without hearing chiplets being mentioned.

At a time when end markets are splintering and more designs are unique, chiplets are viewed as a way to rapidly build a device using exactly what is required for a particular application. They can be chosen on the basis of cost, performance, power, or just about any other metric, providing there are one or more standardized interconnect schemes in place. And they can be used to supplement a vendor’s own IP or design, so there is little worry about the lack of differentiation.

Chiplets also go a long way toward solving one of the biggest problems in advanced packaging, namely there are just too many of them. The OSATs, IDMs and foundries each have their unique approaches, and some have several. That has cluttered the field and created confusion about which one is best for which application.

Chiplets are a way to simplify all of this, and to extend the semiconductor roadmap for increased performance and lower power without putting everything on a planar die. It’s faster to build a device with chiplets, potentially much cheaper, and performance is expected to be greater than, or equal to, current approaches because there is no limit as to how many different processing elements or memories can be slapped together.

The real key is how to put those chiplets together. There already are a number of schemes for this, and there likely will be more. Intel, for example, offers multiple options, from the network-on-chip it acquired when it bought NetSpeed Systems, to its Embedded Multi-die Interconnect Bridge (EMIB). Samsung has been developing a similar technology in the redistribution layer.

OSATs and pure-play foundries, meanwhile, have been focusing on 2.5D and fan-out implementations, as well as some 3D-IC prototypes. TSMC even has a plan to build chiplets into the die at the front end of the line, using a hybrid bonding approach to ratchet up performance. TSMC’s SOIC is a totally different way of thinking about the problem of scaling, because from the outside it will still look and behave like a single SoC.

What’s clear from all of this activity is that the whole industry is taking packaging very seriously these days, and the best way to improve yield in packaging is to have standardized parts and processes. Advanced packaging has been well proven in the market over the past dozen years. And ever since the benefits of scaling began plummeting at 10nm, chipmakers really began changing course and supplementing feature shrinks with multi-die packages. At 5nm, this will be routine.

IEEE has been developing a new roadmap involving heterogeneous integration, and a key piece of that will involve chiplets. It is the only conceivable way to continue achieving the benefits of scaling for a reasonable amount of money and within an acceptable market window. Not everything needs to be developed at the latest process node, and not everything developed at the latest node will be ready at the same time.

If all goes as planned, the effect of all of this will be to democratize advanced packaging, opening up opportunities for smaller companies to compete based upon chiplets rather than full chips. And in a world where many of the hot new markets are still evolving, chiplets could allow companies to update a device to take advantage of a new spec or algorithm by changing out a single hardened part, rather than redesigning the entire device.

This may start out as a single foundry or packaging house’s list of acceptable IP, yet it won’t be long before designs can be customized for different applications, different regions, and different price points. But as this approach evolves, it also will change some of the fundamentals of the semiconductor industry. In the past, getting to market first with the fastest or lowest-power solution was the primary objective, often regardless of the cost. In the future, races will become much tighter, and key pieces of IP in the form of chiplets may come from anywhere.

The beginning of mass customization is on the horizon, and the implications of that are massive.



2 comments

entropyfoe says:

What, no mention of the AMD Ryzen? This is the big success story in the chiplet market. The flexibility to add any number of 8 core chiplets give flexibility for 8, 16, 32, and 64 core CPUs. The current I/O chiplet is still on Global’s 12nm process, so there is another quick upgrade if they update the I/O chiplet to a 7nm process. With chiplets it is easy to mix and match and upgrade parts of the system for flexibility.

Ed Sperling says:

That’s one implementation. Intel is doing chiplets, as well. But the real boost for this market will come when there is a standard interconnect, which would work almost like an API in software. None exists yet.

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