Light In A Package

Silicon photonics is gaining significant traction inside the data center, but creating a simpler method of packaging the laser with other circuitry remains a stumbling block for cutting costs and using this technology across a wider swath of applications. Progress does appear to be on the horizon, even though exact time frames remain unclear.

The advantages of light in communications are well known. Photons are faster, cooler and lower power than electrons. Moreover, there is virtually no limit to the amount of data that light can carry over both long and short distances. Fiber optics have been in commercial use since the mid-1970s, and they have been undergoing improvements ever since. Silicon photonics is a more recent addition, rolling out in something of a piecemeal fashion since the early 1990s.

Commercial usage of silicon photonics started beaming to life last year in data centers, and the overall market for this technology is expected to grow significantly over the next decade. Silicon photonics for applications outside the data center are being readied, as well, with sales expected to starting to ramp slowly sometime in the next few years.

“With tremendous growth in hyperscale data centers, we are near the end of the trough of disillusionment for silicon photonics,” said Eelco Bergman, senior director of sales and business development at ASE. “Over the next couple of years you’re going to see a ramp of activity. There will be much more focus on 100 gigabit/second at distances of up to 2 kilometers. That will be mostly in the data center, rack-to-rack and line-to-line.”

That is consistent with market projections from forecasters such as Yole Développement.

Fig. 1: Silicon photonics market outlook. Source: Yole Développement

That’s just the beginning, too. Michal Rakowski, an IC design specialist for 3D and optical I/O technologies at Imec, provided a glimpse into interconnect speeds based on silicon photonics in various applications. The actual speed will depend on implementations at various process nodes, questions about whether CMOS will support baud rates beyond 50 gigabaud (gigabits/sec), and what type of modulator is used (silicon rings, silicon photonics interposers, etc.)

Fig. 2: Silicon photonics data rates and distances. Source: Imec/Rakowski

Issues still to be solved
The reason for the delay within packages is related to both cost and technical issues. Harnessing light in a package has proven much harder than having an external laser source because the laser typically relies on a III-V material such as indium phosphide (InP), which has to be bonded somehow to CMOS-based circuitry.

This is not a simple problem to solve. In fact, IBM’s Thomas J. Watson Research Center recently developed an adhesive the company described as an “innovation.” Intel has likewise developed its own bonding technology to couple the light source to the waveguides, which are to photons what wires are to electrons.

Another problem is how to attach fiber to the package so that data can move smoothly from one part of the package to another, and from the package out to external fiber optics.

“There are currently two competing approaches for fiber attach—lateral ribbon and vertical grating couplers,” said Gilles Lamant, distinguished engineer at Cadence. “A lateral ribbon allows re-use or evolution of a lot of existing packaging technology, including software, hardware and fabrication technology. A vertical coupling has more potential capacity for high fiber count, but is mechanically different.”

Vertical coupling is more “photonics” in nature, said Lamant, and appears to have a potential for higher fiber count. Lateral/edge coupling appears to be more compatible with electronics, but it could be limited by the number of fibers it can handle.

He noted that 80% of the cost in silicon photonics involves packaging. “The cost of an electric system is the reverse of that. In other words, the place where investment can have the largest impact for photonics systems is in packaging.”

Paul Fortier, advisory engineer at IBM, said that the only way to move from low- to high-volume is through self-alignment, where multiple connections can be made at the same time. That would standardize the design process, lower the package cost, and increase scalability. “For the typical 2D MCM (multi-chip module) package with integrated optics, there are two approaches we’re looking at—fiber and polymer. These also require different gases than those on a semiconductor.”

Intel‘s approach to this problem is quite different, although the goal is the same, namely creating a process that can mass produce these devices to scale like other semiconductors.

Intel starts with a 300mm silicon wafer, and 4-inch indium phosphide wafers. The InP wafers are diced and then flip-chip bonded to the silicon wafers in a single bonding step, according to Robert Blum, director of strategic marketing and business development at Intel Silicon Photonics.

“From there we take it down so only the epi material is left,” Blum explained. “We then write the gratings in silicon and develop the waveguides at the wafer level. The big advantage is that no alignment is necessary because the waveguides and the laser are in silicon, so you can process them at the wafer level. No hermetic sealing is needed.”

Another issue involves how to connect the photonic chip to the networking IC. Today’s solutions require a standard plug with the optics (QSFP) that is connected via long copper traces. With silicon photonics the optics can be placed in close proximity to the networking silicon, reducing the overall power budget and space required.

Fig. 3: External connection of photonics package. Source: Intel.

Intel’s big achievement last year was that it moved into production with a mature process and high yield, Blum said. That is a first step in dropping the price of silicon photonics to a level where it is competitive with existing packaging.

“Packaging is a limiting factor,” said Ashkan Seyedi, photonics research scientist at Hewlett Packard Labs. “To do exascale computing, the operating expense has to be low enough. We have pushed everything, but there is still room for efficiencies in the packaging. There are millimeters of potential savings in optical assembly. And if we can move from 2.5D to 3D, we can bring optics under CMOS.”

Seyedi noted that changes to the interconnect and the basic technology for the lasers can further reduce the cost.

“Quantum dots are much more efficient than quantum well technology,” he said. “As quantum wells heat up, you get blurring. Quantum dots blur less. Quantum dots are more stable almost by a factor of 10, but it’s much harder to get it right.”

The supply chain adds yet another challenge. “The supply chain is long and fragmented today,” said ASE’s Bergman. “As we go forward, customers will want the supply chain to contract. So you have the s doing silicon, ASICs, PICs (photonics ICs), substrate and wirebonding, while the downstream component vendors are doing the optical components and the fiber.”

He said the most likely path is for OSATs to expand downstream and to acquire the necessary equipment and expertise. But while this market is growing, it’s still a work in progress, and companies that intend to stake out a role in photonics are moving cautiously.

“The package itself is not like a molded BGA,” said Bergman. “You have an interconnect between the photonics and the substrate. Today, there is a connector in front, but as we go forward, you want to increase the density. 2.5D and fan-out will be key capabilities. You want to move from a connector to PCB/package-based modules. Silicon optical benches are like through-silicon interposers. Longer-term, you want the optical engine on the PCB with fibers into the front of the blade. The follow-on to that will be optical engines on the package. Package-to-package optical will follow that, but it’s still a ways off.”

Other challenges and unknowns
And then there is debate about how long a photonics chip needs to last. The light source stops producing light over time, which means the entire module becomes useless.

Initial implementations lasted an average of 15 years, which is more than triple the amount of time that data centers actually keep equipment before scheduled upgrades. But the cost was so high that companies began looking at reducing that lifespan to save money, according to industry sources. The current qualification ranges between 7 and 10 years.

But the testing needs to become more standardized along with that, and it needs to be at a system level.

“In microelectronics, the device is the biggest cost,” said IBM’s Fortier. “In photonics, packaging test is the biggest cost.”

Blum said Intel’s approach is to do a full test at the wafer level after the III-V material has been attached and processed. Not everyone is taking the same approach, though.

“In addition to the optical challenges, there are also challenges on the 3D-IC (electronics) side of the equation when building a photonics system,” said Cadence’s Lamant. “On the electronics side, we are re-using much of the investment we have made in advanced packaging for other applications to address the challenges with photonics systems. This re-use of existing applications is being done by both design companies, and at the foundry level.”

Market drivers and tooling
Silicon photonics currently does not require the most advanced manufacturing process nodes. That means a variety of EDA tools should work to develop these chips. That isn’t always the case, however.

“There are some unique challenges with temperature variation, simulation, and parasitics—particularly line-edge roughness on the waveguides,” said Juan Rey, senior director of engineering for Calibre at Mentor, a Siemens Business. “Line-edge roughness has a discrete representation. It looks like waviness on the sides of the waveguides. Thermal is another matter. Everything is tuned precisely to the wavelength of the signal. If you shift the temperature, it will have an impact on the wavelength. There is a well defined pitch on how it will respond. A few degrees can make a difference.”

Rey noted that photonics IC developers currently are using optical proximity correction tools, as they would for a standard semiconductor. But he said the increase in complexity will likely push them toward inverse lithography. That reticle enhancement technique, which has been available for about a decade, enables an optimal photomask pattern by improving the process and depth of focus of lithography.

Photonics chips may be one of the key drivers for more widespread use of inverse lithography, as well as a number of other more specialized tools. The EDA industry has been watching silicon photonics closely since the beginning of this decade, and its ramp up inside of data centers may be a signal that this technology is beginning to gain critical mass.

“Photonics is very useful in a number of applications where super high speed is a requirement and the solution was good enough for it,” said Aart de Geus, chairman and co-CEO of Synopsys. ” If you look at the major compute centers, distance is actually starting to matter for a lot of problems. By the time you populate these things with enormous amounts of data—and of course you’d like the data to be as close proximity to computation and vice versa—you start seeing people put more memory on a chip. You’ll also see photonics play a role in the vicinity of those, essentially to accelerate whatever is the weakest link. Another way to describe the industry is the nonstop focus on whatever is the weakest link. The weakest link could be a bug in your software or a really big technology issue that yesterday was immaterial.”

Conclusion
Silicon photonics has come a long way since a few years ago. Over the next few years it is expected to grow significantly as a way to move large quantities of data back and forth inside of datacenters.

But that’s just the beginning of where this technology ultimately is heading. As the technology in silicon photonics matures and as more problems are solved, it likely will play a role in performance-driven applications where price is more flexible, such as servers and networking equipment. And as more of the essential components are moved first to PCBs, and from there to fully integrated packages, photonics will begin to show up in many more devices. The only question is when.

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