Making IC Test Faster And More Accessible: Part 1

The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test vectors and then observe the chip to determine if it exhibits good or faulty behavior. There have been many innovations over the years to make the required testing of chips more tractable. Thanks to innovations from the EDA community, design for testability (DFT) and automatic test pattern generation (ATPG) bring a wealth of approaches to the challenges of IC test.

Current limitations

A staple of these approaches has been scan test. Here, regular flip flops are replaced by scan flip flops that have a dual purpose. In normal operation, they function as any other flop. When scan mode is enabled however, these devices form a chain that allows test vectors to be shifted into the circuit, essentially setting the state of the circuit to known values.  This addresses the controllability part of the test challenge. These flips flops then return to normal operation to allow the circuit to process the known data. Then, scan mode is re-enabled and the internal data values are shifted out of the circuit for examination at the primary output ports of the chip. This handles the observability part of the test challenge.

While elegant in its simplicity, scan-based design has two fundamental limitations. First, the process can be slow, requiring many clock cycles to scan the data in and then scan it out for observation. Remember, you’re running these tests on a production tester. These are very large and expensive pieces of equipment and every second of usage adds additional cost. The second issue is the burden on the I/O subsystem of the chip. Scan design requires a lot of extra pins, and chip I/Os are typically in short supply. So, the additional overhead of supporting scan mode for many chip I/Os can be cumbersome.

There is a third shortcoming with the current approach that is relatively new. As discussed in a prior post, chip testing no longer stops when the part is delivered. With silicon lifecycle management (SLM) on the rise, gathering data from the chip continues throughout its life. The scan testing approach described here relies on a lot of special setup delivered by the IC tester. That equipment is not available in the field.

A proposed solution

A new approach to these problems is hiding in plain sight. I/O is a bottleneck in just about every design, so high-speed protocols have become a popular way to minimize this problem. Just about every chip has a PCIe or USB interface. These are high-performance ports that support various I/O requirements. What if these ports became the new scan ports for designs going forward? Test performance would be enhanced (and costs would go down), pin electronics would be simpler and access to the chip’s test capabilities would be much easier in the field. There is another potential cost advantage by combing scan tests with system-level tests. The figure below illustrates the basic approach of creating another mode for an on-board PCIe interface.

Fig. 1: New test access electronics

Delivering the solution

The Synopsys TestMAX family of test products was launched this past March. It represents the industry’s most comprehensive set of test solutions that address both manufacturing test requirements as well as fast evolving in-system test requirements for automotive and other functional safety related applications. This platform delivers a wide range of test support as shown below.

Two parts of the platform, TestMAX SLT and TestMAX ALE enable this revolutionary new approach to scan test.  Let’s take a look at how this works.

Fig. 2: TestMAX platform

First, TestMAX SLT generates the previously described on-chip interface between the existing high-speed interface (HSIO, e.g., USB, PCIe) and the DFT logic, which is typically composed of scan and compression functions. TestMAX ALE then provides the software interface to the HSIO similar to a software device driver. It enables communication between the operating system file I/O and the software layer driving the host HSIO. The figure below illustrates the complete end-to-end, bidirectional path.

Fig. 3: A new approach to scan test

The benefits of this approach include:

• High-bandwidth test data for low test cost
• Minimal pin count interface that accommodates most designs
• Easily adapts to support different high-speed input-output interfaces (HSIO)
• Simpler automated tester equipment (ATE) pin electronics for reduced tester costs
• Ensures high quality of the device in-system with application of initial manufacturing tests (silicon lifecycle management support)

We’re quite excited about this new paradigm for IC test and believe it will reduce test costs while enhancing quality. We’re also working with test leaders Advantest and Teradyne to ensure a smooth deployment of this new technology.

On to the next problem

I want to leave you with one item to ponder regarding this new approach. The high-speed interfaces described here are quite ubiquitous and the standards supporting them are well-defined. One of the by-products of a ubiquitous standard is a lot of attention, sometimes from the wrong place. So, these interfaces can be the target of hackers. The configuration proposed here, if enabled in the field, can create access to detailed functions inside the chip – not a good thing in the wrong hands.

You shouldn’t worry too much, however. Synopsys has a plan that will address these concerns and I’ll share that in my next post. In the meantime, you can learn more about TestMAX SLT here and TestMAX ALE here.