Manufacturing Bits: April 28

IRPS preview; GAA reliability; bulk vs FD-SOI; AI; 3D.


Gate-all-around reliability
The 2020 IEEE International Reliability Physics Symposium (IRPS) will kick off this week, this time as a virtual event.

IRPS is a conference that focuses on the latest research in microelectronics reliability. The event starts off with keynotes from Infineon, Intel and Texas Instruments.

IRPS also involves a multitude of papers and presentations. On the logic front, for example, IBM will present a paper on a next-generation transistor technology called gate-all-around FETs. IBM will address one type of gate-all-around FET, dubbed nanosheet FETs.

IBM’s paper, entitled “NBTI Impact of Surface Orientation in Stacked Gate-All-Around Nanosheet Transistor,” will address several reliability issues with the technology.

Negative-bias temperature instability (NBTI), a key reliability issue in MOSFETs, is critical. NBTI is an aging mechanism in field-effect transistors that leads to a change of the characteristic curves of a transistor during operation. The result can be a drift toward unintended behavior by functional transistor circuits.

IBM plans to address the NBTI reliabilities for nanosheets. The company will examine the AC and DC NBTI stress and other issues. “We report a thorough study of the NBTI reliability in stacked gate-all-around nanosheet devices with (100) and (110) top surfaces,” according to the IRPS abstract. “We demonstrate that NBTI stresses not only create more permanent defects in (110) than (100) surface due to higher density of Si-H bond but also induce more recoverable damages. Finally, we show that NBTI deteriorates at narrow sheet width in (100) NS devices but is width independent in (110) NS.”

At IRPS, Samsung will investigate soft-error reliability (SER) issues in memories and logic circuits based on 28nm FD-SOI technology compared with bulk finFETs.

Samsung will look at SER based on its own 28nm FD-SOI planar technologies as compared to its 14nm bulk finFETs. The company will compare the two using neutron, alpha, proton, and gamma-ray irradiation tests.

For years, chips based on bulk CMOS have been the mainstream technology for the IC industry. Using bulk CMOS, chipmakers have scaled their devices down to 5nm with 3nm in the works.

In contrast, FD-SOI is a planar technology, which is ideal for low-power apps. Today, 28nm and 22nm FD-SOI processes are shipping with 18nm and 12nm in the works. In a chip, FD-SOI makes use of an ultra-thin layer of silicon over a buried oxide as a means to reduce leakage and variation in chips. FD-SOI also boasts a back-bias feature.

At IRPS, Samsung will look at the alpha-ray-induced soft-error rates or single-event upset (SEU) rates for finFETs and FD-SOI. “Don’t miss this paper if you are involved in the ‘battle’ between bulk vs SOI,” according to an e-mail exchange from IRPS officials. “A Samsung team will compare these two technologies in terms of soft-error reliability, displaying extensive data with interesting differences and the physics behind them.”

AI in fabs
Also at IRPS, Samsung and Korea University will present a paper on using machine learning in fabs.

The paper, entitled “Early Diagnosis and Prediction of Wafer Quality Using Machine Learning on sub-10nm Logic Technology,” will address several issues.

“This paper proposes to use machine learning (ML) methods to predict wafer quality using Fab inline measured items, DC measurements, and DVS (Dynamic Voltage Stress) at wafer sort,” according to the abstract.

“With developed ML approach, the predicted accuracy is more than 80% in 8nm products used in this study. We believe this method can be further fine-tuned to help enable ICs at the high level expected for automotive systems,” according to the abstract. “By assigning predictive rankings, the method also helps enable the best tooling system for higher quality.”

3D reliability
And not to be outdone, Intel will present a paper at the event on the silicon reliability characterization for its Foveros 3D integration technology for logic-on-logic die stacking

Intel recently unveiled a new 3D CPU platform based on the technology. This combines a 10nm processor core with four of Intel’s 22nm processor cores into a package.

“This work presents silicon reliability characterization of Intel’s Foveros three-dimensional (3D) logic-on-logic stacking technology implemented on the 22FFL process node,” according to the IPRS abstract. “Simulations and data demonstrate mechanical strain safe zones around through-silicon vias (TSVs). Evaluations of TSV impact on transistor, interconnect, and defect reliability are reported with a Si technology focus. TSV and bump architectures pass thermomechanical assessments on the final optimized process flow. Foveros 3D stacking technology is shown to exhibit robust silicon reliability.”


Adele Hars says:

Hmm. Aren’t we pretty well past the the “battle’ between bulk vs SOI” stage? Everyone understands that it’s a question of the right technology at the right price for a given application, right? SOI has always been an SER winner (that’s what made it the original choice 30 years ago for mil/aero). But it will be interesting to hear what Samsung has to say about SER now, seeing as they do offer both FD-SOI and (bulk) FinFET.

Leave a Reply

(Note: This name will be displayed publicly)