Manufacturing Bits: Dec. 12

3D diodes
At the recent IEEE International Electron Devices Meeting (IEDM) in San Francisco, the Ecole Polytechnique Fédérale de Lausanne (EPFL) and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) presented a paper on what they call the world’s first back-illuminated 3D-stacked, single-photon avalanche diode (SPAD) in 45nm CMOS technology.

A SPAD is one type of a photodetector. These devices detect low intensity signals down to the single photon level with resolutions. SPADs are used for LiDAR, autonomous vehicles, drones, robots and machine vision systems. They are also used in biomedical imaging and diagnostic systems, such as positron emission tomography, fluorescence-lifetime imaging microscopy, super-resolution microscopy and near-infrared imaging.

At times, though, monolithic or planar SPADs suffer from a loss of photon sensitivity, according to EPFL and TSMC, which is “due to low fill factor or time-resolution uniformity.”

To solve these issues, some have attempted to develop 3D-based SPADs, where devices are stacked on top of each other. This, in turn, could provide increased functionality and better timing performance with lower power consumption. The problem? 3D SPADs sometimes suffer from reduced photon detection probability (PDP) capabilities.

In response, EPFL and TSMC jointly devised a back-illuminated SPAD, which is fabricated in a 45nm CMOS image sensor technology. The device is stacked using a standard 65nm CMOS technology.

In the flow, two separate wafers are stacked on top of each other. The dies are bonded face-to-face. In this approach, SPADs are implemented on the top of the chip. The circuits for data processing, compression and communications are placed on the bottom.

“The SPAD is based on the P+/Deep N-well (DNW) junction, and P-well (PW) guard ring (GR), (which) is implemented to prevent premature edge breakdown, enabling higher electric fields at the active region,” according to the paper from EPFL and TSMC. “A passive quenching and recharge circuit was implemented on the bottom tier, featuring a local 1-bit memory for optical and electrical masking and dual-mode operation: pulse and state. In pulse mode, upon avalanche detection, a signal pulse is generated with fix width. After the dead time, the SPAD is available for a new detection. In state mode, upon avalanche detection, the state of the pixel is held until the next global reset is issued.”

Using this approach, the SPAD achieves a dark count rate of 55.4cps/μm2, a maximum photon detection probability of 31.8% at 600nm, over 5% in the 420-920nm wavelength range, and timing jitter of 107.7ps at 2.5V excess bias voltage at room temperature, according to the paper.

CMOS photon detector
At IEDM, Sony presented a paper on a CMOS photon detector, a technology that could one day replace a photo multiplier tube (PMT).

PMTs are another class of photodetectors that have high sensitivities and resolutions. PMTs are used in medical and life science equipment, but they are bulky and require 1,000V supply voltages. SPADs are being explored to replace PMTs, but “SPADs have serious tradeoffs amongst pixel size, noise floor from dark current, and photon detection efficiency,” according to Sony.

Sony has developed an alternative technology—a non-electron-multiplying CMOS image sensor photon detector. Based on a 90nm process, Sony’s CMOS photon detector features 15μm pitch active sensor pixels with a complete charge transfer and readout noise of 0.5 e- RMS.

The device maintains high signal-to-noise ratio (SNR) despite a reduced pixel size. “Fully depleted photo-diodes of CMOS imagers have a unique feature where the capacitance of the photo-diode does not couple with the capacitance of the pixel amp input node,” according to the paper from Sony. “The photon detection efficiency (quantum efficiency) of CIS with large photodiodes is much higher than PMTs, leading to lower photon shot noise.”

The pixel circuit is a conventional 4T pixel. The pixels are arrayed, resulting in a high conversion gain of 132uV/e-, according to the paper. “The photodiode is expanded to a size of 14.7μm x 13.1μm in a pixel with a pitch of 15μm, resulting in a physical fill factor of 76% without using back illumination. 4 pixels in a column are simultaneously accessed and read,” according to Sony. “The readout circuits, which utilize a single-slope ADC and digital CDS are placed in a 3.75um pitch. Readout noise is dominated by the pixel amp transistor and readout circuits, which are independent of photo-diode size. A 2% reduction in conversion gain due to metal wiring layout occurs in comparison with a reference sample chip with a 3.75μm pixel pitch.”

SOI radiation sensor
Japan’s High Energy Accelerator Research Organization (KEK) has developed a radiation image sensor based on a silicon-on-insulator (SOI) monolithic pixel technology.

A semiconductor radiation image sensor is used in scientific measurements and X-ray applications. In high-energy physics experiments, sensors are used to detect short-lived charged particles, which are generated by high-energy beam collisions, according to KEK.

Today’s radiation image sensors are hybrid devices. They consist of a silicon sensor and a readout device, which are bonded using metal bumps. These devices provide good performance, but they are limited. The pixel size is limited by the bump size of ~50μm. The cost to produce millions of bumps is high, according to KEK.

SOI technology can be used as an alternative approach. KEK has developed a double SOI (DSOI) pixel technology based on a 0.2μm FD-SOI process. “The back-gate effect and the coupling are successfully suppressed and radiation hardness is increased by more than 100kGy (Si) by introducing bias in the middle Si layer,” according to a paper from the organization at IEDM. “In addition, a small pixel size is achieved by using the PMOS and NMOS active merge technique in SOI. This enables a much smaller layout size than that in the bulk CMOS process with the same feature size, while maintaining a high enough analog operation voltage.”