Manufacturing Bits: July 16

Photon chips; French connection; freezing low-k.


Photon Chips
Harvard University, the Massachusetts Institute of Technology (MIT) and the Vienna University of Technology have devised an all-optical transistor controlled by a single photon. The optical transistor could enable the development of photonic quantum gates and deterministic multi-photon entanglement.

For years, researchers have been looking to develop an optical transistor, where a single-gate photon controls a source light beam. By stopping a light pulse in an atomic ensemble contained inside an optical resonator, researchers from Harvard, MIT and Vienna have finally developed the long-awaited optical transistor.

Source: MIT

The switch itself consists of reflective mirrors. When the switch is on, an optical signal passes through the mirrors. When the switch is off, 20% of the light can be transmitted, according to researchers.

A weak gate pulse induces bimodal transmission distribution, corresponding to zero and one gate photons. One stored gate photon produces a five-fold source attenuation, and can be retrieved from the atomic ensemble after switching more than one source photon. Without retrieval, one stored gate photon can switch several hundred source photons.

“For the classical implementation, this is more of a proof-of-principle experiment showing how it could be done,” Vladan Vuletić, the Lester Wolfe Professor of Physics at MIT, on the university’s Web site. “One could imagine implementing a similar device in solid state—for example, using impurity atoms inside an optical fiber or piece of solid.”

French Connection
At one time, Alchimer claimed it would turn the 3D stacked die equipment market upside down. The French company was touting a plating-like deposition technology that would reduce the cost of high-aspect-ratio technology in through-silicon-via (TSV) metallization.

As it turned out, the company’s IP model flopped and the board brought in a new management team late last year. Now, Alchimer is putting a new twist on its model. “We are working on partnerships,” said Bruno Morel, the new CEO of Alchimer, at the Semicon West trade show last week. Morel was a former executive at Applied Materials, Lam and Novellus.

Alchimer also is narrowing its focus on 3D through-silicon vias (TSV) and the interconnect. As part of its renewed efforts, Alchimer recently struck a deal with Imec in an effort to solve one of the pressing problems in the semiconductor industry: the interconnect. Copper interconnects—the tiny wiring schemes in devices—are becoming more compact at each node, causing an alarming increase in the resistance-capacitance (RC) delay.

In the deal with Imec, the focus will be on Alchimer’s Electrografting (eG) product family, which promises void-free filling on 7nm node devices and allows direct copper fill on barrier with no seed layer required for damascene processes. Competing with physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes, Alchimer’s wet deposition technologies are based on a molecular build-up process that breaks through the limitations of dry deposition processes.

Alchimer faces an uphill battle, however. PVD continues to have legs for the interconnect. If PVD runs out of steam, atomic layer deposition (ALD) is waiting in the wings. “PVD has been the technology of choice,” said Kevin Moraes, director of global product management at Applied Materials, in a recent interview. “Even at 14nm, the industry is pushing PVD to work with Ta and TaN. 10nm is still open.”

On another front, CEA-Leti is evaluating Alchimer’s eG and Chemicalgrafting (cG) processes for isolation, barrier and seed layers. When combined, Alchimer’s wet deposition processes have been demonstrated to achieve 20:1 aspect ratios. “Even the most advanced TSVs have aspect ratios of 10:1,” Morel said. “We do it at 20:1.”

Freezing Low-k
Also on the interconnect front, there are two main manufacturing pieces: metallization and low-k dielectrics. For the metallization, PVD continues to extend and enable finer geometries. At 14nm and beyond, however, the industry is now looking at rival tool technologies like CVD and ALD.

Low-k, however, is moving at a snail’s pace and remains stuck amid a slew of challenges. Beyond 20nm, the capacitance increases between the conductive portions of the IC, resulting in loss of speed and cross-talk of the device. To solve the problem, insulating layers of porous low-k dielectrics are integrated using plasma etching. However, plasma etching exposes the dielectrics to active plasma radicals, which then react and change the composition of the dielectric.

There is hope, however. Imec, for one, has developed a cryogenic etching method. The technology is said to protect the surface of porous ultralow-k dielectrics against excessive plasma induced damages.

Etching at cryogenic temperature results in targeted k-value (graph generated at GREMI)

By applying cryogenic temperatures during etching, a condensation of etch products in the pores of the low-k material results in a protection of the dielectrics’ surface. Imec demonstrated the method on a porous organosilicate (OSG) film. “It overcomes the disadvantages of current methods used to reduce plasma induced damage, such as dielectric etch at regular temperatures or low-k repair or high temperature pore stuffing, and it enables sub k=2.0 materials for integration,” stated Zsolt Tokei, program director interconnect at Imec, on the R&D organization’s Web site.

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