Manufacturing Bits: June 30

1μm pitch wafer bonding
At the recent IEEE Electronic Components and Technology Conference (ECTC), Imec presented a paper on a fine-pitch hybrid wafer-to-wafer bonding technology for heterogeneous integration.

Imec described a way to enable hybrid bond pitches down to 1μm using a novel Cu/SiCN (copper/silicon-carbon-nitrogen) surface topography.

Today, the industry is developing or shipping 2.5D/3D packages and others using existing interconnect schemes. The dies are stacked and connected using an interconnect technology called copper microbumps and pillars. Bumps and pillars provide small, fast electrical connections between different devices.

The most advanced microbumps/pillars are tiny structures with a 40μm pitch. Using existing equipment, the industry can scale the bump pitch possibly at or near 20μm. Then, the industry needs a new technique, namely copper hybrid bonding.

Copper hybrid bonding follows a traditional copper damascene flow in a front-end wafer fab. Once a wafer is processed in the fab, metal pads are recessed on the surface. The surface is planarized using chemical mechanical polishing (CMP). Then, the wafer undergoes a plasma activation step.

A separate wafer undergoes a similar process. The wafers are bonded using a two-step process. It’s a dielectric-to-dielectric bond, followed by a metal-to-metal connection.

In some cases, a vendor might develop a wafer with copper pads and a silicon oxide dielectric. But the Cu/SiOx surface may not scale to 1μm pitches due to reliability deterioration, according to Imec.

In response, Imec has developed a modified single hole damascene process. The bottom wafer consists of a series of copper pads, which have been recessed. Each pad is separated by a SiCN dielectric material. The same is true with the top wafer. The difference is the copper pads are protruding. Each pad is separated with the SiCN dielectric material.

The two wafers are then bonded. At the 1.08μm pitch structure composed of 270nm to 540nm nano-pads, the long daisy chains of 70,866 contact links are connected with low resistance and a good bonding interface, according to Imec.

“To attain the protrusion Cu profile, the barrier slurry is properly tuned to reduce the removal rate of Cu to SiCN dielectric. In the other side, the recessed Cu profile concerns more dielectric roll-off at the edge of pad array pattern structures. To minimize the SiCN dielectric roll-off, the hard substrate configuration in the CMP hardware system in combination with the proper slurry enabled stable and controllable performance,” said Soon-Wook Kim, senior integration engineer at Imec, in the ECTC paper. Others contributed to the work.

“To control the stability and performance of Cu nano-pad integration process, the intensive inline atomic force microscopy (AFM) and surface acoustic microscopy (SAM) characterization is used on various test structures before/after wafer bonding,” Kim said. “The surface flatness should be less than 1nm/μm to ensure void free bonding. This surface planarization is readily achieved for Cu pad densities up to 25%. Finally, we have demonstrated the high yield and low resistance performance across the 300mm wafer for hybrid bond pitches between 5 and 1μm.”

Copper nanopaste
At ECTC, IBM presented a paper on a plating-free bumping process using a copper nanopaste with injection molded solder (IMS) technology.

The technology has been demonstrated on a 2D as well as 2.5D packages with stacked die. IBM demonstrated the fabrication of 60μm pitch and 33μm diameter bumps, and 80μm pitch and 46μm diameter bumps.

As stated, the industry is looking at copper hybrid bonding for fine-pitch interconnects in advanced packages. “The Cu to Cu direct bonding technology, however, requires more precise coplanarity control, higher surface cleanliness, increased temperature, time, or pressure, or more specialized environments for obtaining good joints, compared with the solder joint technology. Therefore, the solder joint is still an attractive joining technology even for fine pitch applications, especially for heterogeneous integration which requires joining of multiple devices or components on an organic or inorganic substrate with moderate temperature and pressure in high throughput and yield,” said Toyohiro Aoki of IBM Research, the lead author of the paper. Others contributed to the work.

Instead of a traditional soldering approach, IBM proposes IMS technology. “One of advantages of IMS is the capability of using ternary, quaternary, or higher component alloys even for fine pitch bumps consisting of metal pillars and solder caps. However, the bumping by IMS still requires electro or electroless plating to form the metal pillars prior to a solder injection by IMS. Cu pillar formation without using plating methods can make a bumping process more simple,” Aoki said.

In IBM’s process, the first step is the preparation of a wafer. Then, pillars based on a resist material are patterned and fabricated on the surface. The photoresist thickness after post bake was 33μm with a pattern pitch of 60μm or 80μm.

Between the resist pillars, cup-shaped copper pillars are fabricated. The cup-shaped openings are filled with a copper nanopaste, followed by s pressure-free copper sintering process.

Then, using IMS, molten solder is injected into the space created by the cup-shaped copper pillar. The resist pillars are then stripped, forming solder bumps.

To test the process, IBM devised a 2.5D structure. Two chips were stacked and connected using IBM’s process. “The stacked chip was attached on an organic laminate with 50μm spacers and filled by a conventional capillary underfill. The electrical connection between the top chip and the bottom chip was tested. The size of the top chip was 7.3mm square and 725μm in thickness. The top chip had solder bumps formed by Cu nanopaste and IMS. The pad pitch was 80μm, and 46μm diameter bumps and 46μm square bumps were prepared. An opening of SiN passivation for Al pad on top chip was 48μm square. A size of Ti/Cu protection layers was 55μm square, and that of Ni/Au was 56μm square. The bottom chip size was 10x 10mm and 100μm thick. Bond pad metallurgy on the bottom chip was electroplated Cu with a thickness of 7μm. Organic laminate size is 40 x 40mm and 0.76mm in thickness,” Aoki said.

Stack bonding
At ECTC, A*STAR, or the Agency for Science, Technology and Research, presented a paper on the development of a multi-die stacking approach with copper interconnects using a gang bonding technology.

In gang bonding, dies are stacked on top of each other. Then, they are bonded together using a wafer bonder. This is done without forming any interconnects.

In this process, copper bumps are fabricated on a die with +/-1μm uniformity across the die level. “The Cu bumps on the die are covered with a layer of non-conductive film (NCF) prior to the die stacking process. Non-conductive film offers the protection of the Cu surface and it also helps to clean the copper surface prior to Cu-Cu joint formation,” said Ser Choong Chong of the Institute of Microelectronics at A*STAR, in a paper. Others contributed to the work.

Then, on the wafer, the dies are stacked on top of each other using a conventional flip chip bonder. Then, the dies in the stack are bonded together using a gang bonder for final copper-to-copper joint formation, according to A*STAR.

In gang bonding, the dies are tacked on top of each die in a relative shorter duration as compared to a local thermo-compression process. “There is no need to elevate the bonding temperature to solder melting temperature and no need to cool down for the subsequent die tacking process,” Chong said.

Using this process, A*STAR developed a multi-die stack with 4 dies. Each one is connected. The die size is of 9 x 11 x 0.1mm whereas the package size is 14 x 18 x 0.8mm. The die has depopulated copper bump layout with 25μm diameter at a 100μm pitch.

Related
More ECTC developments
Fan-out gas sensors; glass panel packaging; gel substrates.