Manufacturing Bits: May 20

Brain chips
Pennsylvania State University has developed a technology that could enable futuristic biochips, namely those that mimic the human brain.

In the lab, Penn State combined a thin film of vanadium dioxide (VO2) on a titanium dioxide substrate to create an oscillating switch. VO2 is an exotic material that exhibits semiconductor-to-metal transitions at 68 °C. In the R&D stage for use in ReRAMs, sensors and other devices, VO2 has the quality similar to single crystal silicon.

A cartoon of an oscillating switch, the basis of a new type of low-power analog computing
(Source: Penn State)

Researchers added a series resistor to the oxide device to stabilize the oscillations. When researchers added a second oscillating system, they discovered that the two devices oscillated in unison, thereby possibly providing the basis for chips that mimic the brain.

It will take up to ten years or so to devise a system with 100 million or so closely packed oscillators, which are required to make a so-called neuromorphic computer chip. In theory, a neuromorphic device will use only about one percent of the energy as compared to today’s computers.

This, of course, largely depends if VO2 can be integrated with silicon. “It’s a fundamental building block for a different computing paradigm that is analog rather than digital,” said Nikhil Shukla, a Ph.D. student, on Penn State’s Web site.

The technology could also form the basis of non-Boolean computing. In today’s computing, Boolean logic has two values—ones and zeroes. Small-world networks and neural networks are examples of a non-Boolean computation schemes. “We wanted to use it for a different kind of computing called associative processing, which is an analog rather than (a) digital way to compute,” said Suman Datta, a professor at Penn State.

China’s 3D graphene device
Graphene is a honeycomb lattice made of carbon. The 2D material is strong and conducts electricity, but graphene also lacks a bandgap. This has prevented graphene from becoming a mainstream technology for semiconductor devices.

One group claims to have made a breakthrough in the arena. Researchers from the Chinese Academy of Sciences (CAS) and others have fabricated a vertical device, in which graphene is sandwiched between two asymmetric ferromagnetic electrodes.

Schematic diagram of Ni-graphene-Co sandwich structure of vertical-transport devices (Source: SINANO)

The Ni/graphene/Co device possesses both vertical and the horizontal channels. The spin valve effect was observed when the magnetic field was parallel to the sample. This, in turn, paves the way towards the study of electron correlation and spin transport at high temperatures.

“The measurements of electron and spin transport were performed across the combined channels containing the vertical and horizontal components. The presence of electron-electron interaction (EEI) was found not only at low temperatures, but also at moderate temperatures up to ∼120 K, and EEI dominates over weak localization (WL) with and without applying magnetic fields perpendicular to the sample plane,” according to researchers from CAS.

“Moreover, spin valve effect was observed when (the) magnetic field is swept at the direction parallel to the sample surface. We attribute the EEI and WL surviving at a relatively high temperature to the effective suppress of phonon scattering in the vertical device structure,” according to researchers.

IITC preview
The 17th annual IEEE Joint Conference of the International Interconnect Technology Conference (IITC) and the Advanced Metallization Conference (AMC) will be held in San Jose from May 21-23. Here’s a sneak preview of some of the papers:

In 2.5D/3D designs, through silicon vias (TSVs) typically have a “keep-out zone.” Transistors are not placed in the area. This is due to co-efficient of thermal expansion mismatch between the copper TSVs and silicon. This, in turn, introduces tensile stresses in transistor performance. In one paper, GlobalFoundries will describe a CMP stop layer. In doing so, it introduces compressive stresses on the silicon and compensates for the tensile stresses introduced due to copper TSVs. The result is a near-zero keep-out zone for TSV technology.

Monolithic 3D technology is generating steam. The technology involves stacking transistors on top of each other. In some cases, the TSVs are in the 50nm range. In a paper from CEA-Leti, monolithic 3D provides a 55% area reduction and a 47% energy-delay product improvement for a 14nm FPGA design.

In another paper, AIST describes 8nm wide and 6.4nm thick graphene interconnects with a resistivity of 3.2uohm-cm. This is better than copper with similar dimensions. Separately, carbon nanotubes (CNTs) have been explored as a material for vertical interconnects. CNTs can handle higher current densities than copper and offer ballistic transport. In a paper, Imec demonstrates a 5x improvement in electron mean free path for CNTs compared to previous work.