Manufacturing Bits: Nov. 2

IRDS lithography roadmap; alternative litho techniques.


IRDS lithography roadmap
The Journal of Micro/Nanopatterning, Materials, and Metrology (JM3) has published a paper that outlines the lithography roadmap and the various challenges for the next 15 years.

The paper, called the “International Roadmap for Devices and Systems lithography roadmap,” projects that extreme ultraviolet (EUV) lithography and a next-generation version will remain the main patterning options for leading-edge chips at least until the 0.7nm node in 2034. But the industry faces an assortment of challenges along the way. Other patterning technologies, such as direct write, directed self-assembly (DSA) and nanoimprint, may find a place. All of this could change based on a shift in technology, cost and other factors.

The roadmap will help guide the lithography industry’s plans for future investment and R&D. It also addresses the requirements, possible options, and expected challenges for the next 15 years. Mark Neisser, a lithography veteran and a technology director for the Tan Kah Kee Innovation Laboratory at Xiamen University, is the author of the 2021 lithography roadmap paper. The paper is in the SPIE Digital Library.

The paper reviews and complements the lithography chapter of the annual International Roadmap for Devices and Systems (IRDS) report. The IRDS report also includes topics like factory integration, metrology, CMOS, yield enhancement, and application benchmarking.

The predecessor of the IRDS report was the ITRS or International Technology Roadmap for Semiconductors. Between 1998 to 2015, the ITRS document was produced annually by experts. The goal was to serve as the main reference for various chip and equipment technologies.

The IRDS, the successor to the ITRS, is a set of predictions that provide an outline “to simplify academic, manufacturing, supply, and research coordination regarding the development of electronic devices and systems.” The IRDS roadmap projects future challenges for semiconductors and possible solutions to those challenges. It shows that logic devices will drive shrinking critical dimensions and improvements in patterning for the next 10 years.

Lithography, the art of patterning tiny features on chips, is critical to enable the development of advanced devices. Until 2018, chipmakers used optical-based 193nm wavelength lithography tools to pattern advanced chip features. With various techniques, chipmakers extended 193nm lithography down to 7nm. But at 5nm, it’s too complex to use these techniques.

That’s where extreme ultraviolet (EUV) lithography fits in. Based on a 13.5nm wavelength, EUV lithography simplifies the patterning process, enabling the next wave of chips.

In 2018, Samsung and TSMC inserted ASML’s 0.33 NA EUV scanners for use in manufacturing chips at 7nm. ASML’s EUV scanners enable 13nm resolutions with a throughput from 135 to 145 wafers per hour (wph). Today, Samsung and TSMC are manufacturing 5nm chips using EUV. 3nm is in R&D. Samsung and SK Hynix are ramping up EUV for DRAM production. Intel and others also plan to bring EUV into production.

Going forward, the IRDS lithography roadmap outlines a probable scenario. “Extreme ultraviolet lithography (EUV) systems already in manufacturing use can resolve the smallest line and space dimension on the roadmap if double patterning is used. For contact holes and other hole type levels, double exposure with current tools can already resolve the minimum pitch needed until ‘1.5nm’ in 2025. The ‘1.5nm’ node will be doable with double exposure,” Neisser said in the paper.

Then, in 2025, the industry is expected to migrate to high-NA EUV, a next-generation version that uses a 0.55 NA lens. The current EUV tool uses a 0.33 NA lens.

High-NA EUV is expected to be the main lithographic option for devices until the so-called 0.7nm node in 2034, according to the roadmap. But there are several challenges in bringing up high-NA EUV scanners.

There are other issues. “The major lithographic challenges in the next 10 years are mostly related to noise and defects. Overlay is also expected to be a challenge,” Neisser said in the paper.

Harry Levinson, editor-in-chief of the Journal of Micro/Nanopatterning, Materials, and Metrology (JM3), added: “Roadmaps such as this are invaluable for lithographers. They enable us to have meaningful exchanges regarding technology parameters and targets that would otherwise be too company-sensitive to discuss. They also provide a common reference for people focused on different elements of lithographic technology–equipment, materials, masks, and metrology.”

Alternative litho techniques
The IRDS lithography paper also addresses other so-called next-generation lithography (NGL) technologies. These include DSA, direct-write lithography, and nanoimprint.

DSA isn’t a tool technology, per se. It’s a complementary patterning approach that works with other lithography systems. For example, EUV lithography could be used in conjunction with DSA to enable fine patterns. DSA enables patterns using block copolymers. In DSA, a lithography system forms a pre-defined pattern on a structure. The structure is coated with block copolymers, which then self-assemble into tiny patterns.

Controlling the defects is one of many challenges with DSA. That’s why DSA has more or less lost some momentum over the years. Still, Intel continues to pursue DSA.

Meanwhile, for years, direct-write or maskless lithography was considered the ultimate patterning technology. Originally developed by IBM in the 1980s, direct-write lithography makes use of an e-beam tool that directly patterns tiny features on a wafer.

Direct-write is attractive because it doesn’t require an expensive photomask. But the throughputs for single-beam e-beam lithography are too slow, making it too expensive for volume IC production. As a result, single-beam direct-write tools are relegated to niche applications, such as compound semiconductors and photonics.

To solve the throughput problems, the industry has been developing direct-write e-beam systems that makes use of multiple beams. But so far, the technology is still taking root and has been relegated for niche applications.

Nanoimprint lithography (NIL) is also in various stages of development. In the works since the 1990s, NIL resembles a stamping process. Initially, an e-beam system forms a pattern on a template based on a pre-defined design. Then, a separate substrate is coated with a resist. The patterned template is pressed against the substrate, forming a pattern on the substrate at feature sizes down to 5nm and beyond.

The big challenges with NIL are overlay, defectivity and throughput. At the recent SPIE Photomask + EUV conference, though, Canon presented a paper on a nanoimprint lithography method for achieving sub-3nm overlay. Canon has been developing a nanoimprint lithography system for use in memory production.

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