Mechanical Stress In Semiconductor Development

With the semiconductor industry moving toward 3D DRAM, 3D logic architectures, and 1000+ layer 3D NAND stacks,¹ mechanical failures may become more common. Due to the complexity of these structures, mechanical stress from materials processing has the potential to significantly impact yield. 3D processing techniques (etching, deposition, and related chemistries), as well as material property development and optimization, will need to be adapted to meet the manufacturing requirements of these new 3D structures.

3D NAND subarray structures tilt during slit processing, demonstrating stress evolution, including deformation.

But capturing the impact of mechanical stress during semiconductor process integration is a daunting task. Stress and strain in integrated structures are dependent upon the structure’s material properties and require special techniques to measure. Non-destructive measurement techniques are either low in resolution, or they require large and expensive extreme ultraviolet (EUV) or x-ray sources.

To evaluate stress and mitigate its effects, predictive 3D process models can be used to predict the impact of mechanical stress on yield and performance. These models can capture the evolution of mechanical stress throughout a process integration flow and can be used to optimize material properties, establish optimal process windows, and reduce variability, while minimizing silicon-based build-and-test cycles.

The solution

Semiverse Solutions offers a virtual fabrication platform (SEMulator3D) that can be used to study process integration challenges and optimize and validate processes during high volume manufacturing. An integrated stress analysis module performs mechanical stress analysis during virtual fabrication, capturing how structural deformation evolves through the process flow.

This stress analysis module seamlessly integrates stress analysis into SEMulator3D, providing automated virtual metrology to assist in root-cause analysis. Within the integrated environment, both process and design can be optimized to alleviate the impact of mechanical stress throughout a process flow, reducing the number of design cycles and accelerating yield ramp.

Analyzing stress in GAA FET manufacturing

The figure below displays an example of stress/strain evolution during process integration of a gate-all-around FET (GAA FET) device. During manufacturing, the GAA FET device topology changes with each process step. SEMulator3D stress analysis can display how stress and strain evolve step-by-step during virtual manufacturing steps. This provides a comprehensive picture of stress history and enables the study of “memorization” effects.

More importantly, root-cause analysis of stress issues can be performed by backtracking specific sources of stress, and modifications of material properties or integration choices can be tested to better understand the consequences of these choices on stress and/or deformation in the device.

Stress/strain evolution during process integration of a GAA FET device. 

This is just one example of how virtual fabrication can be used to identify and mitigate stress-based structural failures that impact yield, by backtracking stress results throughout the relevant series of process steps. The same technique can be applied across the manufacturing process for different types of semiconductor chips:

• Logic during critical front end of line (FEOL) stages
• 3D NAND during staircase formation, slit etching, word line, and slit fill processing
• DRAM process flows from the active area through the capacitor process module

Using virtual fabrication in SEMulator3D, the progression of mechanical deformation or stress deformation evolution can be visualized on 3D silicon-accurate device structures. Mechanical stress due to intrinsic stress, thermal expansion, and crystal lattice mismatch can be virtually introduced throughout the material in a 3D structure. Combined with process and design data, mechanical stress and deformation can be evaluated across the entire process flow.

Value of integrated stress analysis

SEMulator3D can execute detailed process integration flows and generate true to silicon, realistic 3D structures. The platform also allows the execution of large, automated Design-of-Experiments to test the impact of process changes on device performance. Automated modeling of stress evolution and deformation during all process steps is supported, along with global virtual metrology and powerful ML/AI to identify root-causes and potential mitigation.

These capabilities provide semiconductor engineers with the ability to address diverse and challenging stress issues during semiconductor development and high-volume manufacturing. Typical use cases include:

• Stress backtracking for source identification and mitigation
• Technology stack optimization for films with tunable stress and low thermal shrinkage
• Monitoring of stress accumulation and release during patterning stack – stress distribution and optimization
• Guiding design and structural assumptions toward robust, low-stress process, materials, and integration schemes
• Identifying and providing an early warning to engineers about structural failures due to stress
• Progressive effect analysis of stress induced deformation
• DTCO for patterning and for preventing wiggling due to spacer deposition

Reference

1. Harmeet Singh, The Path to 1,000 Layers Will Be Etched, Lam Research, https://newsroom.lamresearch.com/1000-layers-NAND-etch