Power integrity analysis identifies key problems in advanced node designs.
By Joel Mercier and Karen Chow
As technologies and foundry process nodes continue to advance, it gets more difficult to design and verify integrated circuits (ICs). The challenges become even more apparent in 5nm and below nodes, and as the industry moves away from fin field-effect transistor (finFET) and into gate-all-around field-effect transistor (GAAFET) technologies. There are many problems that occur at the molecular and quantum level as we continue scaling down to the point where some transistor features are only a few atoms in size. Two of these problems are electromigration (EM) and voltage (IR) drop. Fortunately, these problems can be found and fixed with power integrity analysis.
EM is the movement of metal atoms caused by the flow of current through it. Electrons flow through metal with some velocity, giving them some magnitude of momentum. When these electrons collide with the metal atoms in the interconnects, they can transfer some of their momentum to the atoms, causing the atoms to move. Over time, the movement of these metal atoms creates voids and hillocks in the metal interconnects, as shown in figure 1. Voids can widen and deepen until they create an open circuit in the interconnect, while hillocks can grow high enough to connect to other interconnect wires, creating a short.
Fig. 1: Electromigration can create short circuits between two interconnects through the development of hillocks, or an open circuit through the creation of voids in interconnect.
The risk of EM is directly correlated to the current density of the interconnects. The higher the current density, the more likely EM will affect the design. One of the primary techniques for predicting failure from EM is to simulate currents through the design, then analyze the results to find those locations where the current densities are beyond design limits.
One of the main points of EM failure in ICs is in the vias. Because vias are a point of constriction in the conduction paths, they naturally have an increased current density, just as the water from your garden hose increases in force when you partially obstruct the opening with your thumb. Other factors that influence the occurrence of EM are wire material, wire temperature, and wire size.
Black’s equation, developed by James Black, provides a way to model the mean time to failure of an integrated circuit due to EM [1]. Per Black’s equation (figure 2), the factors that affect EM are: wire material, wire temperature, wire size, and current. Engineers can use Black’s equation to more efficiently design ICs based on the expected usage and application of the device.
Fig. 2: Black’s equation with a description of all the variables it contains.
From Ohm’s law [2], we know that voltage(V) = current(I) * resistance(R). As current flows through a resistor, it creates a voltage drop (IR drop).
Electrical power is needed for a chip to function. With device scaling, transistors and wires get smaller, but the chip dimensions remain relatively the same. This dichotomy means wires become narrower, but stay the same length, which increases the parasitic resistance of those wires. Due to this resistance, the voltage in the path from a supply pin to the input of the cell in which it must be used decreases (drops) over that path (figure 3). For example, moving a 28nm chip design to 7nm results in approximately a 10x increase in wire resistance. This resistance continues to get exponentially larger as we move to even smaller nodes.
Fig. 3: Distributed parasitic resistance in the interconnects between a supply pin and a cell reduces the original supply voltage. The voltage the cell receives is the supply voltage minus the IR drop in the wire.
There are two types of IR drop in a design, static and dynamic. Static IR drop is the voltage drop that occurs when there is a constant current draw, due to parasitic resistance in the wires. Dynamic IR drop is a voltage drop cause by high switching activity of transistors. Many transistors switching at the same time can cause locations of high current on the chip. Dynamic IR drop, in particular, has been getting worse as power consumption and chip frequency increase at advanced nodes [3].
EM and IR drop have always been present in ICs. However, with the device scaling of today’s advanced process node designs, they have become serious threats to IC reliability. As transistors continue to be scaled down, interconnects and other components must be scaled down as well. Decreasing the size of interconnects increases the resistance and current density, making the interconnect more susceptible to EM and a higher IR drop.
As voltage drops, transistors operate more slowly, which can cause timing violations. These violations can slow down performance in the final chips. If timing violations are not found and fixed before the chip is fabricated, the chip may not meet its design specifications, which can result in having to sell the chips at a reduced price for less-demanding uses, reducing profits. Even worse, timing violations can cause functional failures of the chip, which can result in entire lots of chips that don’t even make it to market [4]. Both outcomes are very costly to chip manufacturers, making IR drop analysis an essential step in the IC verification flow before fabrication.
One other issue that comes with scaling transistors down is self-heating. Self-heating is the increase in heat trapped in a device due to high current density and poor heat dissipation. This is especially evident in silicon-on-insulator (SOI) FINFET and GAAFET technologies (figure 4). These form factors have limited paths to allow heat to escape the device, due both to their three-dimensional geometries and because the thick buried oxide layers are not very thermally conductive. As a result, much of the internal heat in the device is transferred into the metal interconnects, which speeds up EM.
Fig. 4: SOI finFET and GAAFET devices contain a buried oxide layer that impairs heat dissipation.
A 7nm finFET will, on average, heat up 12K from ambient when in use, and a 5nm GAAFET will heat up 17K. Those heat-up rates decrease the EM-induced time to failure of interconnects by up to 38% in SOI finFET, and 45% in GAAFET technologies [5].
Both EM and IR drop violations can be identified using power integrity analysis, which takes as inputs both the simulation results and extracted parasitics of a design. The design is then analyzed based on desired current ratings to determine the places in the design that may be susceptible to EM, IR drop, and other electrical effects.
When EM and IR drop violations are found in a design, there are a couple of actions designers can take to resolve these violations. Since both types of violations are affected by high resistance in the wires, most techniques for reducing their effects (without changing the manufacturing process) focus on reducing resistance, which will reduce the current density in a wire.
One approach is to increase the width of the wires that have violations. Increasing the cross-sectional area of the wire reduces resistance. However, this solution is often at odds with design scaling, especially at advanced nodes.
Another common technique is to increase the number of vias during a transition between metal layers. Vias are a point of constriction because the surrounding metal is a greater width than the via, increasing the resistance and current density in the vias. If we increase the number of vias where there is a high amount of current, there will be more paths for the current to flow through, reducing overall current density.
Other ways to reduce resistance of a wire are by reducing the resistivity of the metal or by reducing its length. Copper interconnects can withstand about five times the current density of aluminum, providing lower resistivity and a higher resistance to EM. Designers can also limit EM effects by utilizing the Blech length, which determines a certain ratio between line length and current density where no EM will occur. The Blech length is typically between 10 and 100 microns.
As process technologies and transistors scale down, interconnects and other features must be scaled accordingly. The increased resistance and current density that come with device scaling create reliability concerns, specifically with EM and IR drop. The impact of these effects has been accelerated with the transition to 7nm and 5nm SOI finFETs and GAAFETs. EM can cause interconnects to deform and create short or open circuits in the IC, while IR drop can cause an IC to fall below design specifications, or even fail, if there is too much resistance in a wire in some part of the IC.
EM and IR drop effects can be identified, analyzed, and mitigated using power integrity analysis. By taking a parasitic netlist and circuit simulation as its inputs, a power integrity analysis tool can evaluate an IC layout and pinpoint areas of the layout containing EM/IR issues. With that information, designers can make layout modifications that can reduce or eliminate EM and IR drop effects in the manufactured chip.
A more detailed discussion can be found in the technical paper, Analyzing EM/IR in IC design layouts to ensure reliability and performance.
References
Karen Chow is a principal product engineer for the Calibre Design Solutions group in Siemens Digital Industries Software, focusing on driving parasitic extraction development in analog and RF design flows. Prior to joining Siemens, Chow worked in the telecommunications and EDA industries, designing analog ICs and supporting EDA tool development. She received her Bachelor of Science degree in electrical engineering from the University of Calgary, and her MBA from Marylhurst University.
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