Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to design optimization and finishing. Automated context-aware checking provides designers with actionable results that improve both debugging efficiency and verification precision.

Introduction
Many people tend to associate design complexity only with advanced nodes, but the truth is, design complexity is growing at all nodes. More and more functionality is being added to designs, new and expanding applications are being incorporated, and designers are stretching design margins to the limit as they seek to leverage every last bit of usable design area.

As designs become more tightly packed, local effects that were previously marginal, or even non-existent, may suddenly become significant or critical. These context-aware effects, which result from a combination of both physical and electrical conditions, require a new type of verification strategy—one that can detect and combine the physical layout of a component with its electrical implementation, and analyze that information to evaluate a wide range of design conditions, from advanced design rule compliance to circuit and reliability verification to design optimization and finishing.

Context-aware checking
For as long as there have been design rules, there have been design rule checks, and for as long as there have been netlists, there has been electrical verification, but these were historically distinct and separate verification flows. However, designers are facing new verification challenges in today’s tightly-packed designs that cannot be solved by either of these verification techniques in isolation.

Context-aware checks merge physical and electrical information to determine design rule compliance. They first emerged as an extension to design rule checking (DRC) spacing checks, but have quickly evolved to address a variety of demanding process and reliability requirements for today’s designs. Figure 1 demonstrates how context-aware checks can go beyond simple polygon width, spacing, and run length requirements, and take into consideration the nets enclosing those polygons and their associated voltage domains when determining DRC compliance [1-4]. For example, the voltage-aware spacing check must have both the physical layout data and domain voltage information to accurately determine the required spacing between the polygons. This type of check contributes to improved net reliability without over-constraining the spacing and overall design area.

Figure 1. Context-aware checks use both physical and electrical data to calculate compliance.

Similarly, the design-critical patterns that impact yield are no longer driven just by optical proximity correction (OPC) hotspots or silicon failures, but also by electrically-aware patterns, such as differential pairs, current mirrors, silicon photonics structures, and others.

However, while context-aware checks add immense value to design verification and optimization, early implementations relied on manual annotation and scripting. Designers had to analyze and select the applicable electrical characteristics, cross-reference them between front-end and back-end, and manually add marker layers and layout annotations, all of which is both time-consuming and subject to human error. Given the growth in the type and number of context-aware checks, and the tight, market-driven schedules most companies face, the manual approach is simply not viable in most design companies [4].

Automated context-aware flows
Similar to the evolution in the design flows that required new layout-aware design techniques, where both the front-end (schematic) and back-end (layout) are implemented simultaneously to account for layout proximity effects and stress parameters, automated context-aware flows link the electrical and topological checks and cross-reference them to the layout side. Uses of automated context-aware checking include advanced physical verification, circuit and reliability verification (e.g., context-aware latch-up, electrical overstress, electrostatic discharge) [5], DFM and design finishing (e.g., net-aware annotation and filling, via strapping fill, orientation-aware fill, multi-patterning coloring) [6,7], and yield/failure analysis (Figure 2). These context-aware flows are now integrated with every stage in the design and verification cycle.

Figure 2. Automated context-aware checking and design enhancement can be used at every step of the design, verification, and test cycle.

For example, designers can combine electrical and physical pattern matching functionality to detect a differential pair in the netlist (across different hierarchies), and cross-reference the pair to the layout to perform advanced checks (e.g., layout variants of the same schematic topology, symmetry, matching, common centroid, etc.). These symmetry checks are isomorphic, meaning they can work on single component electrical matching, or analyze the X/Y and common centroid symmetry of a group of components. Figure 3 illustrates the functional flow of a common centroid check.

Figure 3. Automated context-aware check flow for common centroid assessment.

Another example of context-aware flows is failure analysis, in which hotspot/defect results can be associated with their interacting nets, devices, and even their voltage domains. This data provides the end-user with actionable feedback that improves the quality, accuracy, and turnaround time of debugging.

Summary
Context-aware verification flows were developed to solve demanding design and manufacturing challenges in both established and emerging nodes.  Automated context-aware checks have been achieved by leveraging new EDA tool capabilities and advanced integrations across multiple verification domains. With capabilities such as automated voltage propagation, topological pattern recognition, and integration of both physical and electrical information within a logic-driven layout framework [8,9,10], automated context-aware checking can be leveraged for fast, accurate, context-aware validation in all phases of design verification.

Utilizing flows that leverage existing DRC, pattern matching, and layout vs. schematic (LVS) capabilities with integrations to other electronic design automation (EDA) tools, designers can make educated decisions, receive actionable results, and more easily and accurately adjust layouts based on both the electrical and geometrical aspects in a design, improving both debugging efficiency and verification precision. As products with greater complexity are developed, and consumers demand increasing performance and reliability, the use of automated context-aware checking has become an essential best practice for providing reliable and timely products to the market.

References
[1]  Dina Medhat, “Automated Solution for Voltage-Aware DRC,” EE Times. December 23, 2015. https://www.eetimes.com/author.asp?section_id=36&doc_id=1328540

[2]  Mentor, a Siemens Business. “Running Voltage-Aware DRC Checks using Calibre PERC”

[3]  Matthew Hogan, “Improve Reliability with Accurate Voltage-Aware DRC,” Mentor, a Siemens Business. September, 2013.

[4]  Sherif Hany, “Calibre PERC advanced voltage-aware DRC delivers exacting accuracy for today’s complex designs,” Mentor, a Siemens Business. December, 2018.

[5]  Matthew Hogan, “Automated and Context-Aware Latch-Up Checking with the Calibre PERC Reliability Platform,” Mentor, a Siemens Business. June, 2017.

[6]  D. Kim, E. de la Garza, M. Ibrahim, S. Hany Mousa, M. Hogan, “Improving Analog and RF Fill Generation using Calibre PERC, YieldEnhancer and Pattern Matching,” 2017 Design Automation Conference (DAC). June 2017, Austin, TX.
http://soiconsortium.eu/wp-content/uploads/2018/10/2017_0616_GF-Fill-Flows-with-Calibre-DAC2017_v1.4-FINAL.pdf

[7]  Sherif Hany, “Combine Pattern Matching with DFM to Optimize Layouts,” Electronic Design. April 26, 2018. https://www.electronicdesign.com/embedded-revolution/combine-pattern-matching-dfm-optimize-layouts

[8]  Kollu, K., Jackson, T., Kharas, F., Adke, A., “Unifying Design Data During Verification: Implementing Logic-Driven Layout Analysis and Debug,” 2012 IEEE International Conference on IC Design & Technology (ICICDT), pp. 1-5, May 30 2012-June 1 2012. https://ieeexplore.ieee.org/document/6232874

[9]  P. Gibson, Ziyang Lu, F. Pikus and S. Srinivasan, “A framework for logic-aware layout analysis,” 2010 11th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, 2010, pp. 171-175. https://ieeexplore.ieee.org/document/5450415

[10]  M. Hogan, S. Srinivasan, D. Medhat, Z. Lu and M. Hofmann, “Using static voltage analysis and voltage-aware DRC to identify EOS and oxide breakdown reliability issues,” 2013 35th Electrical Overstress/Electrostatic Discharge Symposium, Las Vegas, NV, 2013, pp. 1-6. https://ieeexplore.ieee.org/document/6635948