A new technical paper titled “Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform” was published by researchers at MIT, Oak Ridge National Laboratory, and Ericsson Research.
According to this MIT news article:
“Growing 2D materials directly onto a silicon CMOS wafer has posed a major challenge because the process usually requires temperatures of about 600 degrees Celsius, while silicon transistors and circuits could break down when heated above 400 degrees. Now, the interdisciplinary team of MIT researchers has developed a low-temperature growth process that does not damage the chip. The technology allows 2D semiconductor transistors to be directly integrated on top of standard silicon circuits.”
Find the technical paper here. Published April 2023.
Zhu, J., Park, JH., Vitale, S.A. et al. Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform. Nat. Nanotechnol. (2023). https://doi.org/10.1038/s41565-023-01375-6.
Leave a Reply