Georgia Tech researchers: the nonvolatile capacitive crossbar array was experimentally demonstrated for in-memory computing
Abstract
“Conventional resistive crossbar array for in-memory computing suffers from high static current/power, serious IR drop, and sneak paths. In contrast, the “capacitive” crossbar array that harnesses transient current and charge transfer is gaining attention as it 1) only consumes dynamic power, 2) has no DC sneak paths and avoids severe IR drop (thus, selector-free), and 3) can be fabricated on top of complementary metal–oxide–semiconductor (CMOS) circuits for 3D-stacking. For the first time, ferroelectric Hf0.5Zr0.5O2 (HZO) capacitive crossbar arrays are experimentally demonstrated. Asymmetry of the HZO electrode interfaces leads to small-signal capacitance on/off ratio >110% that can achieve read-disturb-free operation. The vector matrix multiplication (VMM) experiments are conducted on the fabricated capacitive crossbar array, showing a linear weighted sum versus numbers of input or on-state weight. The array-level VMM operation could maintain weight pattern reprogramming after 1) thousands of 1 ms/3 V pulses and 2) an extrapolated 10-year retention at 85 °C. Array-level circuit simulation at 22 nm node shows the energy consumption of a capacitive crossbar array is 20–200× lower than the resistive crossbar array counterpart. Moreover, analog-shift-and-add circuits are designed for multibit weight summation, achieving 16.6% less area and 26.9% lower energy consumption than digital-shift-and-add circuits.”
Find the open access technical paper here. Published Feb. 2022.
Hur, J., Luo, Y., Lu, A., Wang, T., Li, S., Khan, A.I. and Yu, S. (2022), Nonvolatile Capacitive Crossbar Array for In-Memory Computing. Adv. Intell. Syst. 2100258. https://doi.org/10.1002/aisy.202100258.
Visit Semiconductor Engineering’s Technical Paper library here and discover many more chip industry academic papers.
Leave a Reply