One PHY Does Not Fit All

Consumers expect their battery-operated mobile devices to be faster, smaller and more reliable while providing greater functionality at a reduced cost. Most of all, consumers demand longer battery life and 24/7 access to data. To meet these demands, consumer system-on-a-chip (SoC) designers must make tradeoffs between features, performance, power and cost.

Enterprise SoC designers have their own set of specific feature, power, performance and area constraints, with some taking higher priority than others. As a result, the serializer or deserializer (SerDes) PHY IP implemented in the SoC is no longer a “one-size-fits-all” solution.

In selecting the optimal SerDes PHY IP for consumer and enterprise SoCs, it’s important to know the evolutionary and revolutionary approaches to balancing features, performance, power and cost. In addition, it’s important to consider the relevant technology trends and market drivers.

Mobile and Portable Consumer Technology and Trends
The need for higher bandwidth has grown over the years as more data is generated and moved around the global network. Consumers’ video data now accounts for approximately 80% of the global network traffic. Portable wireless and battery-operated devices generate 50% of this traffic. The many integrated semiconductor parts required in consumer mobile and portable devices that we carry every day, like cell phones and cameras, is expected to contribute significantly to the 6 to 10% semiconductor unit growth worldwide in the next few years.

IC manufacturers are successfully contributing to this growth by offering high-density, high-performance SoCs that include more functionality, at a lower cost. However, shrinking transistor dimensions have caused the leakage power to increase more than the dynamic power in the last few process nodes. Dynamic (active) and static (standby) power consumption are the main components of total power.

28 nanometer (nm) planar processes offer the necessary scaling performance improvements for the evolution of consumer mobile products. (See Figure 1). However, because leakage power is a growing concern, designers must explore other process alternatives and architectural techniques to reduce power. Moving to 16nm or 14nm technology nodes may be too costly for some designs. Because of this, an evolutionary shift is on its way for protocols and standards such as PCI Express, Serial ATA (SATA) and others to support more aggressive power management features and techniques—especially as the number of I/Os per SoC expands to meet the need for higher bandwidth.

Figure 1: SoC process migration – consumer mobile and portable applications.

Cost is another key concern for SoC designers of consumer applications. One way to lower cost is by reducing area. An area-optimized SerDes PHY IP requires smaller area, which directly results in lower cost. Lower-power SerDes PHYs reduce cooling costs and potentially enable the use of lower cost packages. Furthermore, minimizing the need for external components reduces the total system cost. Fully silicon-verified and electrostatic discharge-tested SerDes PHY IP enables faster SoC integration time and eliminates reliability concerns while lowering the overall solution cost.

High-End Enterprise Computing and Networking Application Technology and Trends
Enterprise applications require higher performance, higher reliability and higher bandwidth, as well as around-the-clock availability. Enterprise SoCs are complex designs that tend to implement more features. Power and cost remain a concern, but maintaining high performance and data rates take priority. The SoC must be optimized for active power, as at times more than half of the energy cost is due to cooling. In addition, higher power consumption limits the number of features that can be integrated in a SoC.

The need for higher data rates and silicon densities have forced a shift from 28nm, to 16/14nm, and even smaller technology nodes, as shown in Figure 2. In addition, it’s becoming more beneficial to switch to transistor architectures such as multiple-gate MOSFET (finFET) or even the ultra-thin body, fully depleted silicon on insulators (FD-SOI). Leakage power is addressed in these process technologies as they inherently have much lower leakage over process and temperature variations.

Figure 2: SoC process migration — high-end computing and networking products.

Finding the Optimal SerDes PHY IP
Consumer applications need a narrower range of standards that are optimized for power, performance and area. Enterprise applications need a broader range of electrical standards and higher bandwidth. Lowering leakage power remains a higher priority for SoC designers of consumer applications whereas lowering dynamic power and increasing performance are key requirements for enterprise SoC designers.

Recognizing that “one size fits all” is no longer adequate for selecting the optimal SerDes PHY IP, Synopsys has developed a broad range of multi-lane, high-density PHY IP consisting of PCI Express, SATA, Ethernet standards and other protocols. These PHYs offer 10 Gbps data rates for consumer applications and up to 16 Gbps for enterprise applications. Available across a wide range of process nodes, Synopsys’ SerDes PHY IP enables designers to utilize the power, performance and cost advantages of a particular process technology for their target applications.