tag: Synopsys

Verification Of Multi-Cycle Paths And False Paths
By Joe Mallett - 24 Sep, 2020 - Comments: 1

All chip designers know that they must take special care to avoid metastability problems when they have multiple, asynchronous clock domains. In contrast, a design in which all clocks are synchronous may appear simple. Logic synthesis ensures that the shortest paths between registers don’t have races and that the longest paths fit within the target cycle time. However, single-clock design is ... » read more

New Uses For Assertions
By Ann Mutschler - 24 Sep, 2020 - Comments: 0

Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification engineers have used assertions in specific ways. First, there are assertions for formal verification, which are used by designers to show when something is wrong. Those assertions help to pinpoint wh... » read more

Productivity Keeping Pace With Complexity
By Brian Bailey - 24 Sep, 2020 - Comments: 0

Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo... » read more

Blog Review: Sept. 23
By Jesse Allen - 23 Sep, 2020 - Comments: 0

Arm's Matthew Mattina introduces a method to reduce the cost of neural network inference by combining both low-precision representation and the complexity-reducing Winograd transform while maintaining accuracy. Cadence's Paul McLellan checks out some of the biggest machine learning systems from Nvidia, Google, and Cerebras that were presented at the recent Hot Chips. Mentor's Robin Bornof... » read more

RISC-V: What’s Missing And Who’s Competing
By Ed Sperling - 23 Sep, 2020 - Comments: 0

Part 2: Semiconductor Engineering sat down to discuss the business and technology landscape for RISC-V with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are exc... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 18 Sep, 2020 - Comments: 0

Security Synopsys’ Software Integrity Group published the results of a security survey that looked at the ways organizations across industries are handling their software security initiatives and how to improve them. The Building Security In Maturity Model (BSIMM) version 11 (BSIMM11 Study) describes the work of 8,457 software security pros. FinTech — the technology that “follows the mon... » read more

Week In Review: Design, Low Power
By Jesse Allen - 18 Sep, 2020 - Comments: 0

Nvidia will acquire Arm from SoftBank in a $40 billion deal. Nvidia says that Arm will continue to operate its open-licensing model while maintaining global customer neutrality. SoftBank acquired Arm in 2016 for $32 billion; it also holds an ownership stake in Nvidia that is expected to remain under 10%. The deal does not include Arm's IoT Services Group. The acquisition will need to pass regul... » read more

Custom Designs, Custom Problems
By Ed Sperling - 16 Sep, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Blog Review: Sept. 16
By Jesse Allen - 16 Sep, 2020 - Comments: 0

Cadence's Paul McLellan checks out what's new for TSMC's advanced packaging solutions and the ultra-low power, RF, eNVM, and CMOS image sensor specialty processes. Mentor's Ron Press points to an automated solution to measuring pattern value that provides a consistent, “apples to apples” assessment of patterns detecting defects based on the likelihood the physical defects occurring. S... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Sep, 2020 - Comments: 0

Silvaco acquired the assets of Coupling Wave Solutions (CWS), including IP, patents, and analysis technologies. CWS provides tools for system-level interference analysis of complex SoCs that integrate analog, RF, and digital blocks. Silvaco said that the acquisition expands the company’s portfolio to address RF SOI (Silicon on Insulator) substrate analysis to accurately model and simulate noi... » read more

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