tag: ANSYS

Next-Gen Distributed Machine Processing
By Rama Nemalikanti - 08 Aug, 2013 - Comments: 0

By Rama Nemalikanti The gate count increase of chip designs, especially for mobile application processor system-on-chips (SoCs), is being closely tracked to help guide the development of supporting design and simulation tools. However, sign-off quality power integrity analysis requires the inclusion of the entire integrated circuit (IC) design, along with its associated package and printed cir... » read more

SoC Power Integrity And Sign-Off For 28nm Designs
By Various Writers - 08 Aug, 2013 - Comments: 0

A presentation discussing how RedHawk enables physical design weakness identification, automatic repair the source of the supply noise, analyze impact of dynamic voltage drop on timing and jitter, verify power and signal EM, and provide a model of the chip’s PDN for system-level analysis. To view this video tutorial, click here. » read more

Mixing Custom And Standard Parts
By Ed Sperling - 08 Aug, 2013 - Comments: 0

By Ed Sperling The amount of third-party and re-used IP content in an SoC is on the rise, but once a decision to buy vs. make has been made it doesn’t always stay that way. In fact, chipmakers are swinging the pendulum back and forth across a variety of chips, building IP themselves, standardizing on another vendor’s IP, then sometimes rolling it back the other way. The reasons are usua... » read more

IoT Brings Power Awareness Opportunities
By Ann Mutschler - 08 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler Limited only by imagination, the “Internet of Things” (IoT) is breathing new life into many segments of the semiconductor industry that are losing hopes for growth in the SoC market. In virtually any vertical market space, from automotive to consumer, from industrial to networking, one can imagine the potential for what IoT concepts could realize including higher ... » read more

Experts At The Table: Who Pays For Low Power?
By Ed Sperling - 26 Jul, 2013 - Comments: 1

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director ... » read more

New Silos Form In IC Industry
By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling For the past couple of decades corporations around the globe have been focused on down silos. In fact, it has become a mantra. It’s considered essential for making established corporations even more successful, and it’s almost always at the center of turnaround plans for troubled companies. Moreover, across a full spectrum of companies, it’s regularly cited by management c... » read more

Experts At The Table: Automotive Electronics
By Ann Mutschler - 25 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss the opportunities in automotive electronics with Alexandre Palus, principal SoC architect at Altera; Aveek Sarkar, VP of product engineering & support at Apache; Mladen Nizic, engineering director, mixed signal solution at Cadence; and Stephen Pateras, product marketing director, silicon test solutions at Mentor Graphics. Wh... » read more

Experts At The Table: Who Pays For Low Power?
By Ed Sperling - 19 Jul, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director o... » read more

RTL Design-for-Power In Mobile SoCs
By Preeti Gupta - 11 Jul, 2013 - Comments: 0

If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz. Mobile system-on-chips (SoCs) continue to clock faster and pack more functionality, yet are required to consume lower power for battery life and thermal considerations. Power consumption is a k... » read more

RTL Design-for-Power Methodology
By Various Writers - 10 Jul, 2013 - Comments: 0

This paper presents a design-for-power methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power. To download this white paper, click here. » read more

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