tag: Cadence

Why Chips Are Getting Noisier
By Brian Bailey - 13 Jun, 2019 - Comments: 4

In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Waiting For Chiplet Interfaces
By Brian Bailey - 13 Jun, 2019 - Comments: 0

There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

Revolution By Evolution: Getting To The Next Technology Breakthrough In Analog Simulation
By Cadence - 12 Jun, 2019 - Comments: 0

Recent technology developments, advanced-node adoptions, and Moore than Moore designs have forced analog and custom IC designers to adopt new design practices that benefit from these advancements. These changes have resulted in the need to simulate larger designs with more post-layout parasitics. In addition, many custom IC designs such as flash memory, MRAM, sensor arrays, etc., now require SP... » read more

BiST Grows Up In Automotive
By Ann Mutschler - 12 Jun, 2019 - Comments: 0

Test concepts and methods that have been used for many years in traditional semiconductor and SoC design are now being leveraged for automotive chips, but they need to be adapted and upgraded to enable monitoring of advanced automotive systems during operation of a vehicle. Automotive and safety critical designs have very high quality, reliability, and safety requirements, which pairs pe... » read more

Blog Review: June 12
By Jesse Allen - 12 Jun, 2019 - Comments: 0

Synopsys' Taylor Armerding warns that city and state governments aren't learning from history when it comes to ransomware, and despite numerous examples of recent attacks are not implementing proper security measures or even keeping systems patched. Cadence's Paul McLellan shares highlights from the recent Embedded Vision Summit, including how light can be used at femtosecond intervals to ob... » read more

Data Confusion At The Edge
By Ed Sperling - 11 Jun, 2019 - Comments: 0

Disparities in pre-processing of data at the edge, coupled with a total lack of standardization, are raising questions about how that data will be prioritized and managed in AI and machine learning systems. Initially, the idea was that 5G would connect edge data to the cloud, where massive server farms would infer patterns from that data and send it back to the edge devices. But there is far... » read more

5G Drives New Test Approaches
By Kevin Fogarty - 11 Jun, 2019 - Comments: 0

Test/validation providers are claiming steady progress in the race to deliver 5G network components that support millimeter-wave as well as lower-frequency networks. Going from a state of no existing off-the-shelf test equipment suitable for 5G standalone new radio (NR), test companies are introducing equipment that can handle mmWave component testing on a limited scale. 5G is a next-generat... » read more

Week In Review: Design, Low Power
By Jesse Allen - 07 Jun, 2019 - Comments: 0

M&A Infineon Technologies will acquire Cypress Semiconductor for $23.85 per share in cash, or $10.1 billion. The deal will place Infineon as the number eight chip manufacturer in the world based on 2018 revenues and create an automotive powerhouse, making the combined company the largest supplier of chips to the automotive market. Infineon sees potential to reach into new industrial and co... » read more

Machine Learning Drives High-Level Synthesis Boom
By Kevin Fogarty - 06 Jun, 2019 - Comments: 0

High-level synthesis (HLS) is experiencing a new wave of popularity, driven by its ability to handle machine-learning matrices and iterative design efforts. The obvious advantage of HLS is the boost in productivity designers get from working in C, C++ and other high-level languages rather than RTL. The ability to design a layout that should work, and then easily modify it to test other confi... » read more

Training Tomorrow’s Chip Designers
By Ann Mutschler - 05 Jun, 2019 - Comments: 1

With technology advancing rapidly and the growing number of open R&D projects, there is an expanding need for qualified engineers. To make this possible, practical education needs to start much earlier than after graduation. One the best ways the EDA and semiconductor industry has embraced is encouraging engineering students to cooperate with experienced engineers, technologists and indu... » read more

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