Week In Review: Design, Low Power

Infineon buys Cypress; massively parallel circuit simulation; HDL synthesizer; semi-formal RTL X handling; MIPS Open ISS.


Infineon Technologies will acquire Cypress Semiconductor for $23.85 per share in cash, or $10.1 billion. The deal will place Infineon as the number eight chip manufacturer in the world based on 2018 revenues and create an automotive powerhouse, making the combined company the largest supplier of chips to the automotive market. Infineon sees potential to reach into new industrial and consumer IoT applications, as well. The deal is expected to close by the end of 2019 or early 2020.

Cadence unveiled the Spectre X Simulator, a massively parallel circuit simulator capable of solving 5X larger designs when compared to previous simulation solutions. The tool also improves simulation time, allows for accuracy/performance tradeoffs and is integrated with Xcelium Parallel Logic Simulation for mixed-signal verification.

Aldec added a high-speed HDL synthesizer, SyntHESer, to its HES-DVM emulation tool. The company says SyntHESer performed 10x faster in an in-house bench test than a leading standalone synthesis tool when handling identical blocks of HDL for a circa 45-million-gate Deep Learning Accelerator (NVDLA) design. Multiple synthesis jobs can be run concurrently on HES-DVM, and for the NVDLA design SyntHESer took less than 20 minutes to synthesize the HDL.

Avery Design Systems debuted a tool to perform high accuracy semi-formal based RTL X handling. SymXprop analyzes X propagations in RTL simulations for combinatorial and sequential X inaccuracies using hybrid formal analysis and automatically eliminates these X inaccuracies in RTL simulations. It supports VCS, Xcelium, and Questa simulators. Avery also announced SimCluster GLS to speed up sign-off simulations by 3-5X through gate-level parallel simulation using VCS, Xcelium, or Questa in either multi-core and datacenter cluster compute environments. Its analyzer tool can generate design block workload, port change activities, interconnect complexity between blocks, synchronization analysis, and design hierarchy reports.

ANSYS updated its tool suite, adding a range of new features to its RS 2019 release, including an electronics reliability solutions from the DfR acquisition. Other new features in the electronics and electromagnetics suite include the capability to simulate RF Desense for products that include antennas, RF transceivers, digital data sources and sensors. Additionally, ANSYS Cloud has been added to the electronics suite.

Wave Computing and Imperas Software introduced MIPSOpenOVPsim, a new Instruction Set Simulator (ISS) for the MIPS Open community. Available at no cost, the MIPSOpenOVPsim system architecture simulator implements a complete single-core CPU to test commercial SoC design performance and quality. It supports the MIPS 32 and 64-bit ISA Release 6, licensed under MIPS Open, as well as a range of extensions.

Cadence announced a program to provide cloud customers’ IT teams with assistance provided by authorized partners in deploying Cadence tools in cloud-based environments, as well as customizing the design environment. The Cloud Passport Partner Program includes Rescale, Scala Computing Inc. and Nimbis Services, Inc., as well as academic partners CMC Microsystems and EUROPRACTICE.

Truechip is offering users up to two one-year licenses of its PCIe Gen 3 VIP for free. The free licenses will include all the BFMs, monitors, scoreboards and assertions, coupled with all the advanced features of PCIe, significant extended capabilities such as AER, LTR and a large number of tests cases. The offer also includes a limited version of the company’s TruEYE transaction level debug tool.

Imperas announced an updated simulator for the RISC-V Vector and Bit Manipulation Extensions. Additionally, the ratified RISC-V Specification is now available in the company’s free RISC-V Open Virtual Platform Simulator.

A new organization focused on boosting the adoption of open-source processors has been formed. The OpenHW Group aims to provide a platform for collaboration, create a focal point for ecosystem development, and offer open-source IP for processor cores. “If you’re an SoC designer, you don’t have to design from scratch; we will help you accelerate your design process by supplying you with a growing range of proven processor IP options,” said founder and CEO Rick O’Connor, formerly of the RISC-V Foundation. “For example, for RISC-V-based processors, we’re introducing the CORE-V family of cores, which supports SoC hardware and software designers with a quality and manufacturability assurance when adopting RISC-V processor core IP.” 13 sponsor organizations have signed on, with 25 expected by the end of the year.

Silvaco is providing an open-source, 15nm standard-cell library to Si2. Based on the FreePDK15 process design kit from NC State University, the library is free for non-commercial purposes and is particularly suited to research programs and standards development organizations, according to the company. The Predictive Technology Model from Arizona State University was used in conjunction with the PDK to characterize the 15nm standard-cell library. The library will be available to Si2 members and universities at no fee under the Apache-2.0 open source license agreement.

Achronix selected Rambus GDDR6 PHY for its next-generation Speedster7t FPGA family optimized for AI and ML workloads. Achronix cited the PHY’s ability to support high-performance data acceleration applications at a low cost with low latency.

Wave Computing selected UltraSoC’s embedded analytics and heterogeneous debug technology to test its new TritonAI 64 scalable IP platform for intelligent SoCs. The platform includes three different types of processing engines based on MIPS32 CPU. Wave’s use of the UltraSoC platform will also serve as a reference design for customers needing to validate and debug heterogeneous IP designs.

Faraday Technology adopted Synopsys’ SpyGlass Design Handoff Kit to guarantee design quality at handoff from IP providers and customers and ensure ASIC designs meet design quality requirements before initiating ASIC design service and production. The software and methodologies needed to implement Faraday’s IP and SoC design qualification requirements will also be integrated into the SpyGlass Design Handoff Kit.

Socionext used Cadence’s full-flow digital and signoff tools for the production tapeout of its latest large, 16nm ASIC chip and has built a design environment for its 7nm designs. Socionext cited meeting design productivity goals for the 16nm design and advanced clock synthesis technology that provided PPA benefits to the 7nm design.

Arm and Marvell entered a strategic partnership in which Arm will support Marvell’s R&D in the server processor technology area for at least three more years, including for the next-generation Arm-based ThunderX server technology.

Certifications & Benchmarks
Mentor’s Calibre Physical Verification Suite running on the Microsoft Azure cloud platform successfully scaled out to more than 4,000 CPUs during scaling experiments on 5nm test chips and a full reticle-sized 7nm production design. According to the company, that marked an industry record for an EDA tool scaling a single job on Azure. Mentor and Azure plan additional experiments to demonstrate further scaling and establish recommended chip design sizes to help mutual customers achieve their target runtimes in cloud deployments.

Synopsys is teaming up with GloablFoundries on a portfolio of IP for the 12nm Leading-Performance (12LP) FinFET process, including Multi-Protocol 25G, USB 3.0 and 2.0, PCI Express 2.0, DDR4, LPDDR4/4X, MIPI D-PHY, SD-eMMC, and Data Converters.

Samsung Foundry certified Synopsys’ Fusion Design Platform for 5nm Low-Power Early (5LPE) process technology. The 64-bit Arm Cortex-A53 and Cortex-A57 processors were used in certification.

SiFive raised $65.4 million in a Series D round, bringing total investment in the RISC-V processor company to over $125 million. Led by existing investors Sutter Hill Ventures, Chengwei Capital, Spark Capital, Osage University Partners, and Huami, alongside new investor Qualcomm Ventures LLC, the round will be used for global expansion and technology development.

Thalia Design Automation raised $2 million in its latest funding round. The funds will be used to accelerate development of Thalia’s Re-use Platform-as-a-Service (RePaaS) solutions for analog IP re-use, design migration and portfolio extension, as well as expansion of both commercial and engineering activities in the UK, USA and continental Europe. The round was led by Deepbridge Capital and with renewed commitment from the company’s existing investor Development Bank of Wales.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.

In 2020 and 2021, DAC will be co-located with SEMICON West at the Moscone Center in San Francisco, CA. However, the research, designer and IP tracks all will be retained under the DAC brand, according to Rob Aitken, an Arm fellow and the 2019 DAC chair. DAC will also have its own show floor.

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