tag: Cadence

Enabling Embedded Vision Neural Network DSPs
By Cadence - 19 Dec, 2018 - Comments: 0

Neural networks are now being developed in a variety of technology segments in the embedded market, from mobile to surveillance to the automotive segment. The computational and power requirements to process this data is increasing, with new methods to approach deep learning challenges emerging every day. Vision processing systems must be designed holistically, for all platforms, with hardwa... » read more

Designing For Ultra-Low-Power IoT Devices
By Ann Mutschler - 19 Dec, 2018 - Comments: 1

Optimizing designs for power is becoming the top design challenge in battery-driven IoT devices, boxed in by a combination of requirements such as low cost, minimum performance and functionality, as well as the need for at least some of the circuits to be always on. Power optimization is growing even more complicated as AI inferencing moves from the data center to the edge. Even simple... » read more

Blog Review: Dec. 19
By Jesse Allen - 19 Dec, 2018 - Comments: 0

Cadence's Dave Pursley checks out the state of high-level synthesis and notes that 39% of survey respondents expect to be using it for the majority of designs within three years. In a video, Mentor's Colin Walls digs into how to measure RTOS performance with a focus on interrupt latency. Synopsys' Taylor Armerding chats with Chenxi Wang of Rain Capital to find what the security landscape will... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Dec, 2018 - Comments: 0

The MIPI Alliance released MIPI I3C Basic v1.0, a subset of the MIPI I3C sensor interface specification that bundles 20 of the most commonly needed I3C features for developers and other standards organizations. The royalty-free specification includes backward compatibility with I2C, 12.5 MHz multi-drop bus that is over 12 times faster than I2C supports, in-band interrupts to allow slaves to not... » read more

The Cost Of Accuracy
By Brian Bailey - 13 Dec, 2018 - Comments: 0

How accurate does a system need to be, and what are you willing to pay for that accuracy? There are many sources of inaccuracy throughout the development flow of electronic systems, most of which involve complex tradeoffs. Inaccuracy leaves an impact on your design in ways you are not even aware of, hidden by best practices or guard-banding. EDA tools also inject some inaccuracy. As the i... » read more

Reducing Latency, Power, and Gate Count with Floating-Point FMA
By Cadence - 12 Dec, 2018 - Comments: 0

Today’s digital signal processing applications such as radar, echo cancellation, and image processing are demanding more dynamic range and computation accuracy. Floating-point arithmetic units offer better precision, higher dynamic range, and shorter development cycles when compared with fixed-point arithmetic units. Minimizing the design’s time to market is more important than ever. Algori... » read more

Blog Review: Dec. 12
By Jesse Allen - 12 Dec, 2018 - Comments: 0

Mentor's Harry Foster checks out how much time and effort is spent on verification of FPGAs and points to the increasing demand for verification engineers. Cadence's Paul McLellan digs into IC Insights' year-end report to see how some of the top semiconductor companies stack up. Synopsys' Taylor Armerding warns that air gaps, a valuable barrier against cyberattacks, are disappearing from ... » read more

Autonomous Vehicle Design Begins To Change Direction
By Ann Mutschler - 06 Dec, 2018 - Comments: 0

Tools that are commonly used in semiconductor design are starting to be applied at the system level for assisted and autonomous vehicles, setting the stage for more complex simulated scenarios and electronic system design. Simulation is well understood for designing automotive ICs, but now it also is being used to design vehicle architectures and sensors, as well as for sensor miniaturizatio... » read more

Mitigating Risk Through Verification
By Ann Mutschler - 05 Dec, 2018 - Comments: 0

Verification is all about mitigating risk, and one of the growing issues alongside of increasing complexity and new architectures is coverage. The whole notion of coverage is making sure a chip will work as designed. That requires determining the effectiveness of the simulation tests that stimulate it, and its effectiveness in terms of activating structures of functional behavior and design.... » read more

Blog Review: Dec. 5
By Jesse Allen - 05 Dec, 2018 - Comments: 0

Mentor's Harry Foster digs into verification effectiveness in FPGA projects and what it means that so many non-trivial bugs escape into production. Cadence's Paul McLellan checks out an effort to integrate photonics with CMOS and find the tradeoffs in three different approaches, plus the view of photonics as applied to military aircraft. Synopsys' Richard Solomon shares some highlights on... » read more

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