tag: Synopsys

3D Stacking: A Reality Check
By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Ed Sperling The first 2.5D and 3D chips are expected to arrive next year, with the mainstream chip market expected to follow in 2013. While this trend already has seen its share of hype, stacked die—whether through a series of TSVs in true 3D or through an interposer layer in 2.5D—is as real as Moore’s Law. In fact, it’s a direct result of Moore’s Law. But unlike the progres... » read more

Solving Memory Subsystem Bottlenecks In 3D Stacks
By Ann Mutschler - 28 Jul, 2011 - Comments: 0

In today’s do-or-die market environment, many SOC makers strive to differentiate their product based upon the rate at which it performs processing. Closely coupled are power concerns that have led to dominance of a multi-core approach, while economic considerations have resulted in the dominance of the Unified Memory Architecture, where all the processors share access to external DRAM. Stacki... » read more

Design For Power Methodology
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2. But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most ef... » read more

Blog Review: July 20
By Ed Sperling - 20 Jul, 2011 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang pays a visit to the Microsoft Store and finds a really smart salesperson who seems to know just about everything there is to know about the products for sale. And yes, that is somewhat unexpected. Cadence’s Jean-Michel Fernandez talks about creating SystemC peripheral models. Fernandez represents Cadence’s Team ESL, which is an interesting developme... » read more

Going With The Flow
By Ed Sperling - 15 Jul, 2011 - Comments: 0

It’s hard to judge things in isolation, but a continuum of acquisitions in the low-power area is proving just how important power considerations have become to hardware and software design, verification and manufacturing flows. Over the past couple of years acquisitions by Synopsys in the virtual prototyping arena, and Mentor Graphics in the test and embedded software area, have included p... » read more

Different Ways To Boost Yield
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler In the race to get products to market with shortening product cycles, steepening the ramp to yield is critical. The introductory phase of a product is the point at which margins are highest and market share can be most easily gained. This is no surprise to chipmakers. What is surprising is just how much more difficult it has become to achieve acceptable yield quick... » read more

SoC Design In 5 Years
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ed Sperling The semiconductor industry is used to looking at changes every couple of years, based upon the progression of Moore’s Law. But look out further, over the next five years when the most advanced process node is somewhere between 14nm and 16nm, and the job of designing and manufacturing an SoC will look very different. At the center of this change are three very significant tr... » read more

Virtual Prototyping Takes Off
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler Skyrocketing software development costs, which for years have been “somebody else’s problem,” are now firmly part of the SoC development teams list of headaches. That has made virtual prototyping far more popular, particularly at 40nm and beyond, where engineers are looking at this approach as a way of managing complexity, doing architectural exploration and eve... » read more

Too Soon For Wide I/O
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler When 3D ICs are prevalent, Wide I/O is sure to be there. But where does the technology stand today? Considering the amount of buzz and hype, it would be easy believe it is being implemented in production designs today. Wide I/O is a very brute-force way of solving the problem of trying to get latency down with a high-speed memory interface, explained Navraj Nandra,... » read more

Managing Physical Effects
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler Managing the physical effects from manufacturing is becoming increasingly critical as designs grow in size and process geometries dive lower. Just keeping track of these effects in a billion-gate design is a daunting task. At advanced manufacturing nodes, the capacitance and inductance effects make the design much harder—and that includes both on-die and off-die ... » read more

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