Possible Uses Narrow For Negative Capacitance FETs

Why technology used in ferroelectric memory may not work in other types of devices.


The discovery of a ferroelectric phase in hafnium dioxide (HfO2) has sparked significant interest in opportunities for integration of ferroelectric transistors and memories with conventional CMOS devices. Demonstrations of “negative capacitance” behavior in particular suggest these devices might evade the 60 mV/decade limit on subthreshold swing, thereby improving transistor efficiency.

However, the physical mechanisms underlying the negative capacitance effect remain unclear. Manufacturers need a better understanding in order to exploit negative capacitance in commercial devices.

The “standard” device considered in most models is a layer of HfO2 or Hf0.5Zr0.5O2 containing a single ferroelectric domain, sandwiched between a metal electrode and a conventional dielectric. The bottom electrode can be either metal (metal-ferro-insulator-metal) or the semiconductor channel of a transistor. Inserting a metal layer between the ferroelectric and the dielectric (MFMIM structure) facilitates independent measurements of the properties of the layers while, at least theoretically, preserving the overall behavior of the combined device.

Researchers at April’s Materials Research Society Spring Meeting in Phoenix sought to determine to what extent these model devices reflect the behavior actually seen in the laboratory. Thomas Mikolajick, scientific director at NaMLab, in Dresden, Germany, described a single-domain ferroelectric as residing in one of two energy states — “up” or “down” polarization — with an energy barrier between them. The energy barrier measures the difficulty of switching from one state to the other, and depends on such physical parameters as the permittivity of the material and the anisotropy of the polarization field.

Switching from one state to the other takes time, during which the voltage across the device is changing more quickly than the polarization. The charge on the ferroelectric capacitor decreases, while the charge on a normal capacitor connected in series increases. This “negative capacitance” effect reduces the subthreshold swing over at least part of a transistor’s voltage-current curve. The price of this improvement, though, is hysteresis.

The relationship between voltage and polarization is different, depending on whether the voltage is increasing or decreasing. Ru Huang, professor and dean of Peking University’s School of Electrical Engineering and Computer Science, said that so far it has not been possible to reduce hysteresis while also reducing subthreshold swing. A better subthreshold swing requires a larger voltage across the ferroelectric, but a smaller polarization charge is desirable to reduce hysteresis.

Instead of switching between “up” and “down” polarization states, though, the material also can split into two (or more) domains, oriented anti-parallel to each other. In fact, according to a detailed analysis by the NaMLab group, the energy barrier between the parallel and anti-parallel orientations is smaller than between the two parallel orientations. Thus, the anti-parallel orientation provides a low-energy pathway between the two single-domain states.

For device designers, this is terrible news. First, the anti-parallel orientation is unstable, so a device built around a multi-domain ferroelectric layer is unlikely to switch in a predictable and repeatable manner. In fact, the formation and movement of domain boundaries appears to be the source of polarization hysteresis. Hysteresis-free switching appears to require a single-domain ferroelectric layer that switches as a consolidated unit.

Second, splitting the layer into multiple domains breaks the equivalence between the MFMIM and MFIM structures, because the internal metal layer changes the boundary conditions for domain formation and movement.

A more complete model, rather than simply assuming a single domain, balances the energy of domain wall formation against the energy barrier between the two single-domain states to determine whether the structure will form multiple domains. The NaMLab group found that the lateral device dimensions, not just the permittivity and anisotropy of the ferroelectric, define the domain wall energy and thus the overall device behavior. The film thickness, surprisingly, is relatively unimportant because only a thin layer near the ferroelectric/dielectric interface will affect the polarization behavior.

According to this model, stable, hysteresis-free steep-slope devices in the MFMIM structure will only be possible at near-single nanometer dimensions, and are probably unrealistic even in extremely scaled CMOS nodes. MFIM structures offer slightly better prospects, but are still extremely challenging.

Whether a narrow theoretical possibility is commercially feasible depends on manufacturing constraints. For example, Mikolajick said that surface energy and oxygen vacancies both play a role in stabilizing the HfO2 ferroelectric phase, and both are highly process-sensitive. Charge trapping in the normal capacitor can screen the polarization/depolarization fields, contributing to unstable behavior.

In summary, both theory and manufacturing constraints would appear to limit the potential for successful integration of negative capacitance FETs. The very characteristics that make ferroelectric memories attractive may become obstacles for other devices.

Fig. 1: Ferroelectric polarization as a function of electric field. Source: Wikimedia

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Joe Evans says:

They do not want ferroelectric switching to occur in the gate. Switching cannot occur anyway because the thin conventional dielectric in the gate in series with the ferroelectric capacitor will not store the amount of charge the ferroelectric capacitor will generate if it switches. Back voltage from the dielectric layer will prevent switching unless tunneling occurs through the dielectric material. I am sure tunneling would not be a good thing for transistor operation. Think of a Sawyer-Tower circuit where the sense capacitor is far smaller in value than the ferroelectric capacitor of the circuit. This means they actually will want a thicker ferroelectric layer, not thinner.

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