Process Window Optimization Of DRAM By Virtual Fabrication

New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges. Industrial focus has shifted from the scaling of predictable unit processes in 2D structures to the more challenging full integration of complex 3D structures. Conventional 2D layout DRC, offline wafer metrology, and offline electrical measurements are no longer sufficient to achieve performance and yield goals, due to the complexity of these new 3D structures. Trial-and-error silicon engineering is also becoming prohibitively expensive, due to the time and cost of wafer-based testing.

“Virtual fabrication” is a potential solution to this problem. Virtual fabrication software can create a digital equivalent of an actual semiconductor device, by modeling integrated process flows in a digital environment. The software supports process variability testing, integration scheme development, defect analysis, electrical analysis and even process window optimization. Most importantly, it can predict the downstream ramifications of process changes that would otherwise require build-and-test cycles in the fab.

A DRAM demonstration

We will use SEMulator3D, a virtual fabrication software platform, to demonstrate how virtual fabrication can efficiently solve complex semiconductor manufacturing and yield challenges. We will model the effect of etch tool variations (such as material selectivity or flux distribution) on device electrical performance. A simple DRAM device study will be used to highlight the effect of gate etch behavior and etch step characteristics on electrical performance and yield targets.

The workflow will follow a typical 4-step virtual fabrication sequence:

1. Nominal process steps and device geometry information are entered into the software. This allows the software to generate a 3D predictive model of the device that can be further calibrated.

Fig. 1: Once the model information is entered, it displays the capacitor contact as shown. At this point, electrical analysis can be performed, and the edge effect of the capacitor can be investigated.

2. Metrics of interest are established to qualify the structural or electrical behavior. These may include virtual metrology, 3D DRCs (design rule checks) and electrical parameters such as V_th.

Fig. 2: SEMulator3D identifies device electrodes in a 3D structure and simulates device characteristics similar to TCAD software, but without the need for time-consuming TCAD modeling.

3. A design study is executed in the software. This uses a DoE (Design of Experiments) to identify important parameters and includes data and sensitivity analysis to aid in optimizing process development and/or design changes.

Fig. 3: Engineers can analyze any metrology in SEMulator3D to identify important parameters, revealing corner cases as shown (encircled in red) above.

4. Finally, Process Window Optimization is performed to provide an optimized value for each process parameter, maximizing the percentage of the selected parameters that fall within the yield spec.

Process model optimization to satisfy an electrical performance target

Fig. 4: Depiction of the analytics workflow in SEMulator3D, including the PWO feature.

In this example, we will optimize manufacturing processes to target a specific electrical performance. We will choose a specific electrical value and optimize our process steps around this target. Each process step parameter will be varied to search for process conditions that meet the electrical performance target. In our study, we have chosen V_th (threshold voltage) as our target, with a value of 0.482V. Using regression analysis in the software, we can identify three process parameters (Spacer Oxide Thickness, Spacer Oxide Depth and High K Thickness) that are significant in terms of their impact on the threshold voltage (see figure 5). This step is followed by Process Model Calibration (PMC) using the same regression data, which ensures the accuracy of the process model prior to optimizing these three important process parameters to achieve the given V_th targets.

Fig. 5: Optimization results using Vth as the target, with optimized parameters.

Process Window Optimization (PWO) to set the optimal process parameter ranges

Process Window Optimization (PWO) can substantially reduce the number of pre-production wafers needed for offline testing by using a structured and step-by-step methodology to perform virtual experimentation. It can predict maximum yield (success rate within lower and upper limit ranges, see figure 6) for existing processes under consideration. More importantly, it can re-determine nominal process conditions and variation control requirements to achieve maximum success rate (or yield).

After the important parameters are identified, a new virtual Design of Experiments (DOE) will be executed to find parameter values that meet performance and yield requirements. The experiment must include a defined search space (or range) for each of the selected parameters. To obtain statistical significance, the simulated experiment is run many times across the user-defined search space. The PWO algorithm then provides an optimized value for each process parameter, maximizing the percentage of the selected device parameter(s) that meet the target device specification (“inSpec%”).

As shown in figure 6 (left), assuming a 0.5nm, 1.0nm and 0.2nm standard deviation for the three parameters (spacer oxide thickness, spacer oxide depth and high K thickness), respectively, the PWO system reported an increase in metrology in-specification percentage from 34.668% to 49.997%, after changing the nominal values of all process parameters as a result of the maximization process. Moreover, as shown in figure 6 (right), reducing the standard deviation of the most influential parameter (3.20: BWL High K deposition thickness), from 0.2nm to 0.13nm increased the metrology in-specification percentage (yield rate) to 89.316% when the success rate target was set at 88%. A dramatic improvement in overall yield was possible by controlling the variability of equipment responsible for High K gate oxide deposition. This is extremely valuable information for a process integration engineer seeking to improve yield.

Fig. 6: Left: New Mean Values Identified for Spec % maximization (deposition thicknesses and etch depth). Right: Required Range Determined: Standard deviation on the BWL High K Thickness to meet success rate >88%.

Virtual fabrication saves time & cost

Process parameter settings are established during early stages of semiconductor technology development, even before the first wafers are fabricated. Virtual processing can help validate these initial process parameter values without the time and expense of creating and testing real wafers. SEMulator3D’s new Process Window Optimization technology offers the following advantages during semiconductor process development:

• Predicts yield accurately for existing processes
• Retargets nominal POR (process of record) parameter values to maximize yield
• Determines the key process steps that most impact yield
• Isolates failing case (out-of-spec) conditions, and identify the root cause of these failures
• Accelerates process development, by avoiding trial-and-error silicon engineering

Download the white paper, “Process Window Optimization of DRAM by Virtual Fabrication,” to learn more.

References
[1] https://www.coventor.com/paper/speeding-up-process-optimization-virtual-processing
[2] https://www.coventor.com/blog/control-variability-semi-process-window-optimization