The Quest For Faster Data Throughput On A Chip

By Ed Sperling

As with all network topologies, the general rule is the faster the better.

Jack Browne, VP of sales and marketing at Sonics, said his customers are asking for higher-speed interconnects. “Right now we’re at 300MHz,” he said. “They want to more than double that in the very near future and eventually get to 1GHz.”

Getting to that speed is no simple matter, and several approaches are under consideration.

One approach now being tested is a wireless network on a chip. Intel, STMicroelectronics and Philips are all experimenting with these techniques, sources say. And in the commercial NoC space, companies such as Arteris, Sonics, Silistix and Inventure are working on similar technologies.

Parthe Pande, assistant professor at Washington State University, said it’s too early to tell which approach will win. “This is a big research problem,” Pande said. “On-chip wireless networks are very promising. The big problem there is the on-chip antennae and how small you can make them. One approach is carbon nanotubes, but there are manufacturing problems.”

Serialized packets are another approach, but the tradeoff so far has been increased latency. At least part of that is caused by the complexity of designing systems with dedicated wires, shared busses and segmented busses, as well as algorithms that do not take advantage of all the options. Parallelization remains one of the chief conundrums for all levels of chip and software design.

Brad McCredie, an IBM’s chief architect for the Power6 chip, said to understand what’s happening on a chip becomes evident when you look outside the chip because everything is being consolidated into the chip.

“There’s been a lot of research into optical and on-chip optical, but economics never let that happen,” he said. “Whether it happens in the future we don’t know. But between chips, there is a firm direction toward a parallel bus. In cluster configurations we’re seeing packets.”

He said IBM currently is working on 3GHz packet-switch networks on chip for DARPA. But those chips are using parallelized packet switching. The bulk of the work so far has been serialized, and experts say that has created latency issues.

“The main bottleneck right now is parallelizing software,” said Pande. “This is a very hot research topic right now. Packets are another big research problem.”

One approach is to divide the packets into six parts, slimming down the data being sent and avoiding storage of the packets in cache. But Pande said there is still an enormous amount of work to be done, and so far there is no clear winner emerging from the research.