Ruthenium Interconnects On Tap

Chipmakers’ focus on new interconnect technology is ramping up as copper’s effectiveness continues to diminish, setting the stage for a significant shift that could improve performance and reduce heat at future nodes and in advanced packages.

The introduction of copper interconnects in 1997 upended the then-standard tungsten via/aluminum line metallization scheme. Dual damascene integration schemes replaced “dry” steps like plasma etch and deposition with “wet” processes like electroplating and CMP. At the time, manufacturers were struggling to minimize RC delay in the face of more complex interconnect structures.

Nearly three decades later, the semiconductor industry is at a similar crossroads. Shrinking line dimensions are approaching copper’s electron mean free path. Barrier layers are consuming a larger share of the total available line width. The need for an alternative to copper is growing. Like most radical changes, though, manufacturers hope to delay this one as long as they can.

Results presented at the recent IEEE Interconnect Technology Conference showed that opportunities for copper optimization remain.

Getting the most out of copper
As interconnects shrink, interfaces and their properties become more relevant to electrical performance than the bulk material properties. Jongmin Baek, senior engineer at Samsung Semiconductor, and his colleagues looked specifically at how optimizing the barrier and etch stop layers needed for copper can improve overall performance. For example, in a contact metal-spacer test vehicle, the group used a sidewall plasma pre-treatment to reduce the sidewall barrier thickness by a third, improving contact resistance by 2%. [^⁠1]

The Samsung researchers paid particular attention to the via bottom barrier. Because metal vias rest on metal lines, this barrier is not needed as either an electrical insulator or a diffusion barrier. It exists only as an artifact of the sidewall deposition, yet it can account for more than 60% of via resistance. Selective deposition methods often are used to reduce via bottom deposition. In Baek’s work, a polymeric inhibitor improved selectivity relative to the self-assembled monolayers that are commonly used, giving a 20% resistance reduction.

Modern interconnect schemes depend on a variety of carbon-doped oxides for the “C” part of the circuit’s RC delay. Less dense materials are attractive because they have lower dielectric constants (k). Additional work by Samsung’s Kang Sub Yim considered the depletion of dielectric surface carbon by plasma etching.[^⁠2] Etching damage to low-k dielectrics raises the effective dielectric constant, and therefore the capacitance of the circuit. Higher-density materials, typically with k values above 3.0, are more resistant to plasma etching damage, potentially giving them a lower effective k value in sub-30nm features. For features smaller than about 30nm, surface carbon depletion has a larger impact than the bulk dielectric constant.

Yim’s group also used surface silylation to restore etch damage. However, Baek pointed out that surface treatment of the dielectric sidewalls risks contamination of the exposed metal at the via bottom. Instead, Baek’s group used a thermal recovery process with proprietary chemistry to revert the post-etch Si-OH terminated surface to one terminated with Si-CH₃.

Full encapsulation of copper lines includes a metal cap layer — usually cobalt — to reduce electromigration, followed by an insulating etch stop and barrier layer. Due to pitch scaling, these layers are becoming a larger fraction of the total line thickness. To improve the interface with the cap layer, Baek added a plasma pretreatment before the etch stop layer deposition. As a result, they saw a 30% reduction in stress in the copper lines, and a 10% reduction in via resistance. Separately, Yim achieved similar results.

Ruthenium vias, then lines
While all these developments are promising, a long-term successor to copper is still needed. Vias in particular are coming to dominate the overall interconnect resistance because of their small size and their sheer numbers. In the first four or five interconnect levels, the metal lines are very short and don’t contribute much resistance. One alternative, then, is to use a transitional hybrid metallization scheme, combining copper lines with a material like tungsten, ruthenium, or molybdenum for vias.

Simulations at imec showed that using ruthenium vias for the first four layers of the interconnect stack reduces overall resistance by as much as 60%.[^⁠3] To integrate ruthenium vias with copper lines, they suggested depositing a TaN barrier layer on dielectric sidewalls only, landing the ruthenium directly on exposed copper. Any such scheme requires good dielectric surface passivation and good control of ruthenium selectivity. A cluster tool process is preferred, because removing native oxide from exposed copper can damage the dielectric passivation.

Fig. 1: Schematic comparing two self-aligned double patterning processes. Source: imec

Because ruthenium can be deposited or etched in a variety of ways and does not require a barrier layer, it opens the door to much more flexible integration schemes. For example, Giulio Marti, imec R&D engineer, and his colleagues benchmarked three different fully self-aligned via processes.[^⁠4] The first, and most conventional, used EUV self-aligned double-patterning, with the spacer lines that process creates serving to define the metal lines (SADP-SIM). After transferring the spacer pattern to a SiN hard mask, selective RIE etching patterned a ruthenium metal layer, followed by SiO₂ deposition. A highly selective etch aligned the via openings to the remaining SiN features, followed by CVD ruthenium deposition to fill them.

The other two options Marti considered, both based on pillar vias, deposited a second ruthenium layer on top of the first, with an etch stop layer separating the two. In these schemes, pattern transfer uses a two-step ruthenium etch. First, a high-aspect ratio etch cuts the desired metal lines in both layers. Then, a spin-on dielectric fills these trenches, with a hard mask on top. Tone-inversion EUV patterns the hard mask to protect the desired via pillars, while the previous etch stop layer protects the underlying metal lines. Marti found that the two pillar via options increased the number of process steps, but increased the process window. In particular, this approach prevents bridging between vias and adjacent lines.

Fig. 1: Schematic comparing SADP-SIM and SADP-SID processes. Source: imec

Another alternative, proposed by Chen Wu, another imec R&D engineer, and his colleagues uses the SADP spacers to define the dielectric features, rather than the metal.[^⁠5] In this SADP-SID scheme, a hard mask material is deposited between spacer pillars, which are then removed. Though this approach adds process complexity, it means that metal features are defined directly by the mask, giving designers more flexibility and control over feature dimensions.

Regardless of the specific approach, though, Wu emphasized that optimized ruthenium etch and deposition processes will be critical. Tapered Ru profiles, footings at the base of ruthenium features, and incomplete removal of the TiN adhesion layer can reduce the spacing between adjacent lines, leading to leakage.

An integration scheme is just the beginning
A successful process integration scheme requires careful attention to all the component layers. For ruthenium, that optimization process is just beginning. Jack Rogers and colleagues at TEL’s Albany Technology Center investigated the effects of adhesion layer process conditions on ruthenium’s deposition behavior. Ruthenium films on PVD and ALD TiN had different grain orientations, different grain orientation distributions, and different resistivities. Larger and more uniform Ru grains appear to reduce resistivity, at least when grains are smaller than the overall interconnect dimensions.[^⁠6]

Though ruthenium interconnects will require fewer auxiliary layers than copper — that’s part of the point — the re-introduction of metal etch and dielectric fill processes are sure to keep process engineers busy for years to come.

References

1. Jongmin Baek, et al., “Interface engineering for performance and reliability boosting of logic devices,” International Interconnect Technology Conference, San Jose, 2024, paper 2.5.
2. Kang Sub Yim, Jong Min Baek, Hoon Seok Seo, “Advanced interconnect capacitance and interface engineering beyond 1.4nm Logic Devices,” International Interconnect Technology Conference, San Jose, 2024, paper 2.1.
3. Marleen H. van der Veen, et al., “Low Resistance Stacked Via Metallization for Future Interconnects,” International Interconnect Technology Conference, San Jose, 2024, paper 12.1.
4. Giulio Marti, et al., “Redefining 2-Level Semi-Damascene Interconnect Technology: Benchmarking three different Fully Self- aligned Via options,” International Interconnect Technology Conference, San Jose, 2024, poster 9.1.
5. Chen Wu, et al., “Demonstration of MP18-26nm Ru Semi-Damascene Spacer-is-Dielectric SADP Integration,” International Interconnect Technology Conference, San Jose, 2024, poster 9.3.
6. Jack Rogers, et al., “Process Control for the Modification of Ruthenium Resistivity in Scaled Subtractive Interconnects,” International Interconnect Technology Conference, San Jose, 2024, paper 2.4.

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