Signoff Intensity On The Rise

By Ann Steffora Mutschler and Ed Sperling

Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow.

While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. This sounds relatively benign, until you consider the enormity of the task.

“This is a big shift for the industry and for physical design implementation,” said Jean-Marie Brunet, product marketing director for design for manufacturing and place-and-route integration at Mentor Graphics. “10nm is really a big inflection point. You have to modify designs to handle billions of shapes in different colors.”

It’s so enormous, in fact, that many chipmakers aren’t rushing forward. “We’re seeing a lot of customers stay at 28nm longer,” said Brunet. “FD-SOI is getting interesting traction for low power and mobile applications. But for customers looking to go to 20/16/14/10nm, it is more painful.”

He noted that confidence in the final product and in signoff have not changed. The tools are still able to handle the job. But so far there is not enough data—because there are so few chips being made at those nodes—to determine whether there are more respins required.

The industry average at the most advanced nodes, according to multiple sources, is about two to three respins per initial design. There are fears it could increase as designs become more complicated, though. As such, getting signoff right the first time – or first few times – is critical. Even coming to a complete understanding of what signoff must include is a necessity.

An engineering source at a large chipmaker noted that there are all sorts of different things that have to happen before a chip can be ‘blessed,’ therefore talking about ‘signoff’ can mean lots of things from timing signoff to static low power verification signoff and ATPG pattern signoff to DFT signoff and logic equivalence signoff.

Specifically, from a timing signoff-centric view, the signoff process, according to Ruben Molina, product marketing director for timing signoff in the silicon signoff and verification group at Cadence includes five main areas of silicon signoff:

1. Timing analysis;
2. Parasitic extraction (digital or analog -transistor level);
3. Power signoff (IR drop, power consumption);
4. Physical verification (LVS DRC);
5. DFM (litho effects, etc.)

“Smaller process nodes, from a methodology standpoint are pretty much the same at 16nm finFET as 28nm,” Molina said. “The problems at 28nm are more severe at 16nm. In particular, design size. Now we’re talking about designs that are averaging somewhere in the 50 million to 100 million cell count. That puts a huge capacity strain on all of the tools that have to do this analysis, and generally the user wants these things to happen as quickly as possible because one of the bad parts about signoff is that you may have this nice schedule that you put together that starts from the very beginning at RTL all the way to signoff. And all of these design phases that happen earlier always seem to extend beyond their allocated time, so by the time you get to signoff, what may have been a two-month thing in the original schedule, now it turns out you’ve only got three weeks to finish it all. You’ve got a compressed schedule, now you’ve got that plus a very large design – much larger than you had at 28nm – and you’ve got to get it all done. The capacity is a byproduct of more gates per square millimeter, which is all having to do with advanced process nodes.”

From a timing analysis standpoint, these advanced nodes are running at much higher frequencies – well above 1 gigahertz – maybe 2 gigahertz or more – with compressed voltage rails so they’re not running at 1 volt. They’re probably running at 0.75 volts or even 0.5 volts. What this means, Molina said, is that whereas previously, “you had a large rail, a large swing and you had plenty of time to get there. The clock edges and signals had really nice shapes to them and you could model these things such that the timing was well correlated to SPICE — but not anymore. These things are very non-linear. They have plenty of waveform shapes that are not regular and it’s a challenge, particularly on the signal integrity side – you’ve got to have a lot of advanced techniques for modeling these waveform effects. It all boils down to trying to achieve the best accuracy as possible.”

Further complicating matters is the issue of process variation, which impacts several signoff areas, Molina pointed out. “On the extraction side at 20nm and below, double patterning is required to manufacture the chip and adds uncertainty to the design. It has to be modeled by parasitic extraction so the tools have to be able to handle this variation to produce parasitic output that can be read by timing tools, and the timing tools have to model it properly to account for the shift in the distance between the lines.”

There are also additional design rule checks at advanced nodes. “We’ve seen a 30% increase in design rule checks between 28nm and 20nm,” said Michael White, product marketing director for Mentor Graphics’ Calibre physical verification products. “We’ve seen a slowing in that rate because at 14/16nm, the back end was still 20nm. But at 10nm, we’re expecting another 25% to 30%. It’s a new process with an important shrink in pitch and the addition of multi-patterning layers. This certainly is getting more complex.”

Directed self-assembly could help in this regard, and it currently is being considered for things such as contact vias, but White said it is not applicable to metal layer lines. He added that the likely insertion point for DSA will be 7nm.

“What we’re also finding that doing things in context becomes more and more important, he added.

Another potential problem is the amount of time it takes to get a wafer back after sign off. At 40/28nm, the average time was about two months. For chips that use more process steps, the time is about four to six months, said Brunet. “If you need a respin and you’re trying to get a chip ready for the holiday market, you may not hit the market window.”

Indeed, a source at a major semiconductor company confirmed that shortcuts will be taken depending on the purpose of the chip. “If you’re going to production, you’re going to take a little extra time and make it right. But if your goal is to meet a market window to deliver samples to a customer and get that business, then you can cut corners.”

For example, the verification team may only close timing to typical; or only close timing to room temperature; or not close timing in test modes if the chip really needs to get out the door.

“We will also waive things that we know are wrong but don’t damage the function of a chip – maybe more damage the lifetime of a chip. Or we won’t optimize for leakage or even power consumption – as long as it won’t melt in the lab, we’re not going to spend the time to do that. Because there is so much firmware and hardware that needs to be designed around our chip we really need our customers to be doing that in parallel with us perfecting it so we take the hit of an extra tapeout and then six months later, and that gives us a chance to incorporate tweaks that the customer may want or fix a bug or two in the production tapeout. But our [modus operandi] is, if it’s a new product, we do not plan to go to production with a first version of it,” the source concluded.

Given the complexities of design at 20nm and below, combined with the additional physical verification requirements of advanced manufacturing, signoff will continue to become more rigorous and thorough.