Supply Monitoring On 28nm & FinFET: The Challenges Posed

A Q&A with Moortec CTO Oliver King.

What are the issues with supplies on advanced nodes?

The supplies have been coming down, quicker than the threshold voltages which has led to less supply margin. In addition to this, the interconnects are becoming thinner and closer together, which is pushing up resistance and also capacitance.

What is the effect of these issues?

In short, it reduces the margin between a design working and not. Design of the layout, in particular, power grids, and careful analysis of power consumption and therefore IR drop has to happen as part of the design, not as a verification at the end.

Also, the need for in-chip supply monitoring, which then in turn controls the chip’s power scheme, is growing. The speed of response for a Dynamic Voltage Scheme (DVS) needs to be such that PMIC control systems can react to supply droops and ‘events’ accordingly without data loss or corruption within the chip. There is also the growing need for high accuracy monitoring to enable fine-tuning of DVS schemes, optimizing power consumption against particular performance profiles. Of course, such monitoring and control schemes must be robust, as overall power control of the chip is at stake.

What about finFET nodes? They have less leakage, right?

There has been a well-publicized swing in power consumption with the move from 28nm to the first finFET nodes. Whereas on 28nm, power consumption was dominated by leakage, on finFET the power tends to be dominated by active switching. Whilst there are obvious benefits to that, there are some subtle effects which need to be considered.

If we consider a thermally stable environment, then leakage is essentially a DC current where the only changes occur with power gating of blocks. This meant it was relatively simple to analyze IR drops around the chip and account for them. However, with the reduction in leakage brought about with finFET, the active power is now dominant which is far more dynamic. This makes it harder to analyze IR drops.

What is the solution?

Depending on the complexity of the end system it may still be possible to design enough margin to cover supply drops, however, the cost of doing so is becoming too high for many applications, as it leaves too much performance on the table for all but the worst corner of silicon.

As such it is becoming more and more common to include some sort of supply measurement circuit within a chip which can allow for real in-circuit measurement of IR drops and supply levels at certain points across the die, and in many cases this information is being used to then feedback control to external PMICs.

How does Moortec address those requirements?

Supplies keep coming down and with the FFC process coming on line and also IoT applications where people are going to want to run at much lower supplies you end up in a position where you are much closer to failure. If you have got a really big supply it’s easy to turn things on and off, the lower the supply gets the harder it is to make that switch.

The key thing for us is that our current product is really geared for IR drop analysis and accurate DC supply measurement. So we can do accurate IR drop measurements with a differential input and we can also measure ground lift, which is the same problem in reverse. Those are the kind of things we can offer with the product.

This can be used to monitor supplies coming in off chip and accurately measures core supply domain voltages. In terms of IR drop, as the gate density increases and the impedance of metal tracking for supplies increases, together with reduced headroom due to supply reduction, we’re seeing a greater problem for the advanced nodes.

Using on-chip core voltage supply monitors allow chip developers to see what the supply conditions are really like and how this compares to simulation results. It can also be used for monitoring events and perturbations (droops in supply).