tag: 10nm

New Architectures, Approaches To Speed Up Chips
By Ed Sperling - 15 Aug, 2016 - Comments: 2

The need for speed is back. An explosion in the amount of data that needs to be collected and processed is driving a new wave of change in hardware, software and overall system design. After years of emphasizing power reduction, performance has re-emerged as a top concern in a variety of applications such as smarter cars, wearable devices and cloud data centers. But how to get there has cha... » read more

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032"... » read more

Stacked Die Changes
By Ed Sperling - 27 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of tha... » read more

Abundant Change Ahead
By Brian Bailey - 06 Jul, 2016 - Comments: 1

There is nobody who would question the amazing ride that semiconductors have been on for the past 50 years. It has been described as the longest running exponential that humankind has ever been a part of—and it is not over yet. Still, the future is very likely to be substantially different from the past. It is almost natural for us to see a trend and assume it will continue. There have bee... » read more

Executive Insight: Raik Brinkmann
By Ed Sperling - 06 Jul, 2016 - Comments: 0

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down with Semiconductor Engineering to discuss where and why formal verification is gaining traction, and how it fits alongside other verification approaches. What follows are excerpts of that conversation. SE: [getkc id="33" kc_name="Formal"] has been around for a whi... » read more

Atomic Layer Etch Heats Up
By Mark LaPedus - 29 Jun, 2016 - Comments: 0

The atomic layer etch (ALE) market is starting to heat up as chipmakers push to 10nm and beyond. ALE is a promising next-generation etch technology that has been in R&D for the last several years, but until now there has been little or no need to use it. Unlike conventional etch tools, which remove materials on a continuous basis, ALE promises to selectively and precisely remove targete... » read more

Interconnect Challenges Rising
By Mark LaPedus - 27 Jun, 2016 - Comments: 1

Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next. At 10nm and beyond, IC vendors are determined to scale the two main parts of the [getkc id="185" kc_name="finFET"] structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects ... » read more

Pathfinding Beyond FinFETs
By Paula Doe - 13 Jun, 2016 - Comments: 0

Though the industry will likely continue to find ways to extend CMOS finFET technology further than we thought possible, at some point in the not-so-distant future, making faster, lower power ICs will require more disruptive changes. For something that could be only five to seven years out, there’s a daunting range of contending technologies. Improvements through the process will help, from E... » read more

Plotting The Next Semiconductor Road Map
By Ed Sperling - 13 Jun, 2016 - Comments: 0

The semiconductor industry is retrenching around new technologies and markets as Moore's Law becomes harder to sustain and growth rates in smart phones continue to flatten. In the past, it was a sure bet that pushing to the next process node would provide improvements in power, performance and cost. But after 22nm, the economics change due to the need for multi-patterning and finFETs, and th... » read more

DAC Day Two: Down To Business
By Brian Bailey - 07 Jun, 2016 - Comments: 0

DAC day two started with a breakfast presentation put on by Synopsys which included guests from ARM, TSMC and HiSilicon. It was titled Collaborating to Enable Design with the latest processors and finFET processes. Collaboration is a word that we hear increasingly when talking about the advanced nodes and today we are truly at the point where one company cannot do it all. Ron Moore, VP of ma... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy